An apparatus for reducing switching time of RF FET switching devices is described. A FET switch stack includes a stacked arrangement of FET switches and a plurality of gate feed arrangements, each coupled at a different height of the stacked arrangement. A circuital arrangement with a combination of a series RF FET switch and a shunt RF FET switch, each having a stack of FET switches, is also described. The shunt switch has one or more shunt gate feed arrangements with a number of bypass switches that is less than the number of FET switches in the shunt stack.

Exemplary embodiments for an exemplary dual transmission gate and various exemplary integrated circuit layouts for the exemplary dual transmission gate are disclosed. These exemplary integrated circuit layouts represent double-height, also referred to as double rule, integrated circuit layouts. These double rule integrated circuit layouts include a first group of rows from among multiple rows of an electronic device design real estate and a second group of rows from among the multiple rows of the electronic device design real estate to accommodate a first metal layer of a semiconductor stack. The first group of rows can include a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors, such as a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor and a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and the second group of rows can include a second pair of CMOS transistors, such as a second PMOS transistor and a second NMOS transistor. These exemplary integrated circuit layouts disclose various configurations and arrangements of various geometric shapes that are situated within an oxide diffusion (OD) layer, a polysilicon layer, a metal diffusion (MD) layer, the first metal layer, and/or a second metal layer of a semiconductor stack. In the exemplary embodiments to follow, the various geometric shapes within the first metal layer are situated within the multiple rows of the electronic device design real estate and the various geometric shapes within the OD layer, the polysilicon layer, the MD layer, and/or the second metal layer are situated within multiple columns of the electronic device design real estate.

A single supply RF switch driver. The single supply RF switch driver includes an inverter, where a first resistor has been integrated within the inverter, and the resistor is connected to an RF switch. In one aspect, the integration of the first resistor within the inverter allows for the elimination of a negative power supply for the inverter, while maximizing the isolation achieved in the RF switch. In another aspect, the driver is a configured to have a second resistor integrated within the inverter. A third resistor is connected between the gate of the RF switch and the inverter. In an alternate aspect, the driver operates from a positive power supply and a negative power supply, thus increasing the isolation in the RF switch even further.

An analog switch includes an input terminal, an output terminal, a common gate, and a common source. The switch includes a current source which has a first input coupled to a first voltage supply, a control input coupled to receive a gate boost signal, and an output coupled to the common gate. The current source supplies a boost gate current to the common gate during a boost period and supplies a reduced gate current during a second period different than the boost period. The switch includes a clamp circuit which has a first terminal coupled to the common gate, a second terminal coupled to the common source, and a third terminal. The switch includes a Vgs detection circuit which provides the gate boost signal responsive to a conduction of current through the clamp circuit.

A switch circuit that can control an electrical connection state without additionally providing a control circuit is provided. The switch circuit includes a transistor, a first switch which control an electrical connection state between a gate of the transistor and a wiring, a second switch, a first diode including an anode and a cathode, a third switch, and a second diode including an anode and a cathode. An electrical connection state between the anode of the first diode and the gate of the transistor is controlled by the second switch, and the cathode of the first diode is electrically connected to a source of the transistor. An electrical connection state between the anode of the second diode and the gate of the transistor is controlled by the third switch, and the cathode of the second diode is electrically connected to a drain of the transistor.

A galvanically isolated switch system and method comprising a plurality of switches having at least one terminal in series electrical connection, at least one control input electrically connected to at least one of the plurality of switches, wherein the at least one control input is isolated from direct current voltages and at least one passive component connected across the plurality of switches.

The invention relates to a driver circuit and an active transmitter device, a series circuit consisting of a first capacitor (4) and a second capacitor (12) being charged to a reference voltage by way of a charging current and the charged capacitors being discharged via the inductor (1) by an oscillating discharge, the discharge being terminated when the current through the inductor has completed an entire oscillation period or a multiple thereof.

Described are apparatus and methods for a load switch with reset and deep sleep capability. The slew rate control methods of the PMOS load switches contained in the load switch configuration is also described. A preferred slew rate control circuit includes a power PMOS transistor that is capable of handling load currents of several amperes along with an integrated controller. The integrated reset and deep sleep functions allow the user to control the basic timing control of the voltages that are required by the system and to save battery power in an extended deep sleep mode such as storage and shipping.

A power breaker apparatus which performs energization and interception between a power supply and a load, includes a current measuring part which measures a current value flowing in a power line supplying electric power from the power supply to the load, an interception part disposed in the power line and including a plurality of semiconductor switches connected in parallel to each other, a control part comparing the current value measured in the current measuring part with an interception threshold value and, controlling on/off of the plurality of the semiconductor switches according to a comparison result, and a failure detection part which detects a potential on an output side of the interception part so that the control part checks for a failure of the semiconductor switches.

Described herein are circuits and methods for improving switch performance when overdriving the gate by adding a delay on a PMOS gate voltage such that it can turn on the PMOS during switch state transition to allow charge/discharge of the switch body voltage faster and it can turn off once the process is complete. For example, back-to-back diodes can be used to separate the PMOS gate and drain. This can reduce leakage current and can reduce or eliminate the potential for breakdown of the switch.