A system including: a first regulator having a first input voltage and a first output voltage; a second regulator having a second input voltage and a second output voltage; a first driver circuit coupled to the first regulator and a switch, wherein the first driver circuit is configured to drive the switch based on the first output voltage; a second driver circuit coupled to the second regulator and the switch, wherein the second driver circuit is configured to drive the switch based on the second output voltage; a driver controller coupled to the first driver circuit and the second driver circuit, wherein the driver controller is configured to select one of the first driver circuit and the second driver circuit to drive the switch based on a control signal; and a switch node coupled to the switch, wherein a switch node voltage at the switch node is a function of the switch being turned on and off.

A selection circuit architecture makes it possible to perform upward and/or downward transitions in sets of sequences of slow and fast phases so as at the same time to solve the problems of inductive switching noise and the problems of currents in the supply rails. This solution has multiple advantages linked to the ease of implementation and flexibility of configurations that are possible for adapting to the specific constraints when designing the circuit.

The present invention provides a driving circuit for a driving hip. The driving circuit includes a bootstrap circuit with a bootstrap voltage terminal. A power terminal of a high-voltage driving circuit is connected to the bootstrap voltage terminal, and a ground terminal of the high-voltage driving circuit is connected to a regulating terminal. A high-side drive circuit includes a high-side pull-up circuit and a high-side pull-down circuit. The driving circuit includes: an auxiliary power terminal; a mirror current source an input terminal of the mirror current source being connected to the bootstrap voltage terminal; a first MOS transistor; a second MOS transistor an equivalent diode component, an output terminal of the second MOS transistor being connected to the regulating terminal through the equivalent diode component; and an equivalent resistance component, the gate of the first MOS transistor being connected to the regulating terminal through the equivalent resistance component.

A circuit includes a current path and a negative bootstrap circuitry coupled to the current path. The current path is coupled between a floating voltage and a reference ground, and includes a current generator coupled through a resistor to the floating voltage at a first node of the current generator. The current generator is controlled by a pulse signal. The negative bootstrap circuitry includes a pump capacitor coupled to a second node of the current generator and to the reference ground. The pump capacitor is configured to provide a negative voltage at the second node of the current generator based on the pulse signal.

A system includes a sensor circuit configured to sense a parameter of a power system having an operating voltage greater than a voltage rating of the sensor circuit, an optical communications circuit configured to receive a sensor signal from the sensor circuit and to generate an optical communications signal therefrom, and an optical power supply circuit configured to receive an optical input, to generate electrical power from the received optical input and to supply the generated electrical power to the sensor circuit and the optical communications circuit. A driver circuit may be configured to generate a first control signal applied to a control terminal of the power semiconductor switch, and the optical power supply circuit may be configured to supply the generated electrical power to the sensor circuit, the optical communications circuit and the driver circuit.

A power converter having a slew rate controlling mechanism is provided. A first terminal of a high-side switch is coupled to an input voltage. A first terminal of a low-side switch is connected to a second terminal of the high-side switch. A second terminal of a first capacitor is connected to a node between the second terminal of the high-side switch and the first terminal of the low-side switch. A first terminal of an inductor is connected to the second terminal of the first capacitor and to the node. A first terminal of a second capacitor is connected to a second terminal of the inductor. A second terminal of the second capacitor is grounded. An input terminal of a current controlling device is connected to a power output terminal of a high-side buffer. An output terminal of the current controlling device is connected to the node.

The disclosure relates to a switched capacitor converter with gate driving circuits for limiting currents provided by switching field effect transistors. Embodiments disclosed include a switched capacitor converter (100), SCC, comprising a plurality of gate driver circuits (101a-d, 200, 300) arranged to provide a gate voltage signal to a respective power FET (102a-d) in response to a respective input switching signal (sw1_in, sw2_in, sw3_in, sw4_in, IN), wherein each gate driver circuit (101a-d, 200, 300) comprises a first gate driver module (206) and a second gate driver module (207), the gate driver circuit (101a-d, 200, 300) configured to operate in: a first mode in which the first gate driver module (206) provides the gate voltage signal to a respective power FET (102a-d, 205) in response to an input switching signal (IN) at an input (203) of the first gate driver module (206) causing the gate voltage signal to switch between first and second voltage rails (201, 202) by operation of first and second switches (208, 209) connected between the pair of voltage rails (201, 202); and a second mode in which, in response to enabling of a current limit switching signal (climit_en), the first gate driver module disables switching of one of the first and second switches (208, 209) and the second gate driver module (207) operates to limit a current provided to the respective power FET (102a-d, 205).

A switch circuit of an embodiment includes a high frequency switch, a first charge pump circuit, a boost signal generation circuit, and a second charge pump circuit. The high frequency switch switches transmission and reception of a high frequency signal. The first charge pump circuit generates a first voltage and a second voltage biased to the high frequency switch. When an edge of an input signal is detected, the boost signal generation circuit generates a first boost signal for temporarily increasing drive capacity of the first charge pump circuit. When the first boost signal is input, the second charge pump circuit operates to temporarily increase the drive capacity of the first charge pump circuit.

A power supply control device controls power supply by switching on or off a first semiconductor switch and a second semiconductor switch that are arranged on a current path. A first diode and a second diode are connected between a drain and a source of the first semiconductor switch and the second semiconductor switch, respectively. Cathodes of the first diode and the second diode are arranged downstream and upstream of the respective anode on the current path. If current flows through the current path even though a microcomputer has given an instruction to switch the first semiconductor switch and the second semiconductor switch off, a first drive circuit switches the first semiconductor switch on.

A power supply circuit configured to generate an output voltage at a target level from an input voltage thereof. The power supply circuit includes a wiring configured to receive the input voltage, a variable resistor provided between the wiring and a predetermined node, a voltage generation circuit configured to apply a voltage at a predetermined level to the predetermined node based on a current from the variable resistor, an output circuit configured to output the output voltage at the target level, in response to the voltage at the predetermined level being applied to the predetermined node, and an adjustment circuit configured to increase a resistance value of the variable resistor in response to a predetermined time period having elapsed since starting of generation of the output voltage.