In an embodiment, a switching circuit is provided that includes a Group III nitride-based semiconductor body including a first monolithically integrated Group III nitride-based transistor device and a second monolithically integrated Group III nitride based transistor device that are coupled to form a half-bridge circuit and are arranged on a common foreign substrate having a common doping level. The switching circuit is configured to operate the half-bridge circuit at a voltage of at least 300V.

An isolated gate driver includes a transformer including primary and secondary windings, a synchronous rectifier connected between the secondary winding and an output terminal of the isolated gate driver, a first switch including a first terminal connected to a supply voltage, a second switch including a first terminal connected to the supply voltage, a first damping resistance connected between a first terminal of the secondary winding and a second terminal of the first switch, a second damping resistance connected between a second terminal of the secondary winding and a second terminal of the second switch, a first inverter including an input connected to the first terminal of the secondary winding and an output connected to a gate terminal of the first switch, and a second inverter including an input connected to the second terminal of the secondary winding and an output connected to a gate terminal of the second switch.

A semiconductor switch drive device (3) includes a drive unit (10), a power supply unit (20), a switch (39), and a control unit (50). The drive unit (10) supplies a control signal to a semiconductor switch (Q) of a main circuit (2) and drives the semiconductor switch (Q). The power supply unit (20) supplies electric power to the drive unit (10). The switch (39) cuts off supply of electric power to the power supply unit (20) by detecting or controlling an overvoltage state on a primary side of the power supply unit (20). The control unit (50) switches a conductive state of the switch (39) on the basis of a voltage of a control terminal of the semiconductor switch (Q).

Disclosed herein are non-limiting examples of voltage generators that use multiple charge pumps coupled in series to generate a targeted voltage. The charge pumps implement multiple charge pump units that reduce the introduction of noise into a circuit in which they are implemented. The charge pumps units work in parallel on different clock phases to reduce spurious noise. This is in contrast to using a single charge pump with a relatively large flying capacitor or a plurality of charge pumps in series. This can, for example, reduce spurious signals or spurs that arise due at least in part to the characteristics of the clock signal. The disclosed technologies may be particularly advantageous for SOI-based components and circuits.

In an embodiment, a semiconductor device is provided that includes a lateral transistor device having a source, a drain and a gate, and a monolithically integrated capacitor coupled between the gate and the drain.

A circuit includes a solid-state relay, a rectifier, and a current transformer-based power supply. The rectifier is adapted to be coupled to the solid-state relay. The rectifier is configured to provide a voltage to an output terminal responsive to the solid-state relay being in an off state. The current transformer-based power supply is coupled to the rectifier and is adapted to be coupled to a transformer. The current transformer-based power supply is configured to provide a voltage to the output terminal responsive to the solid-state relay being in an on state.

A driving device includes a voltage regulator, a voltage generator, and a first NMOSFET. The voltage regulator is coupled between a first high-voltage terminal and the output terminal of the driving device. The voltage regulator receives the first high voltage of the first high-voltage terminal. The voltage regulator steps down the first high voltage to generate a supply voltage. The voltage generator is coupled to a second high-voltage terminal and the output terminal of the driving device. The voltage generator provides a reference voltage for the output terminal of the driving device. The reference voltage is substantially lower than the supply voltage. The first NMOSFET is coupled between the output terminal of the driving device and a low-voltage terminal.

A relay circuit, including a solid state relay switch, connected to a first relay line and to a charging capacitor, and connected to a second relay line. The relay circuit may also include a solid state relay control circuit, coupled between the charging capacitor and the solid state relay switch. The solid state relay control circuit may include a voltage detection circuit, having an input coupled to an output of the charging capacitor, and having an output arranged to generate a LOW voltage signal when a voltage level of the charging capacitor is below a low threshold value. The solid state relay control circuit may also include a zero crossing circuit, coupled to the first relay line and the second relay line, and having an output to generate a clock signal when a zero crossing event takes place between the first relay line and the second relay line.

The present invention relates to a method for recharging an energy store (102) used to drive a power semiconductor switch (100), wherein the energy store (102) and the power semiconductor switch (100) are at the same potential, wherein a switching state of the power semiconductor switch (100) is effected by a controller (204, 712), wherein the controller (204) assigns a respective potential value to the energy store (102) at a respective switching state (202) and wherein, by driving at least one charging switch (112, 114, 122, 132, 142, 152), charging of the energy store (102) is activated as soon as the potential value of the energy store (102) corresponds to a ground potential of a supply voltage (106, 216).

The subject matter of this document can be embodied in a method that includes a voltage regulator having an input terminal and an output terminal. The voltage regulator includes a high-side transistor between the input terminal and an intermediate terminal, and a low-side transistor between the intermediate terminal and ground. The voltage regulator includes a low-side driver circuit including a capacitor and an inverter. The output of the inverter is connected to the gate of the low-side transistor. The voltage regulator also includes a controller that drives the high-side and low-side transistors to alternately couple the intermediate terminal to the input terminal and ground. The controller is configured to drive the low-side transistor by controlling the inverter. The voltage regulator further includes a switch coupled to the low-side driver circuit. The switch is configured to block charge leakage out of the capacitor during an off state of the low-side transistor.