A circuit for regenerative gate charging includes an inductor coupled to a gate of a FET. An output control circuit is coupled to a timing control circuit and a bridged inductor driver, which is coupled to the inductor. A sense circuit is coupled to the gate and to the timing control circuit, which receives a control signal, generates output control signals in accordance with a first switch timing profile, and transmits the output control signals to the output control circuit. In accordance with the first switch timing profile, the output control circuit holds switches of the bridged inductor driver in an ON state for a first period and holds all of the switches in an OFF state for a second period. Gate voltages are sampled during the second period and after the first period. The timing control circuit generates a second switch timing profile using the sampled voltages.

Described herein are reduced-power electronic circuits with wide-band energy recovery using non-interfering topologies. A digital logic driver comprising a pulldown switch, an energy saving component (e.g., inductor) coupled in series with the pulldown switch, and a reference supply connected in series with the energy saving component that is configured to enable the digital logic driver to resonate with a load capacitance and reuse electrical energy at the load capacitance without interfering with a signal path of the digital logic driver.

A DC power distribution system has power sources, a DC power distribution bus with DC bus sections. The system has power switching assemblies to couple one of the DC bus sections to another and a system controller. An inverter is connected to one of the power switching assemblies to supply a consumer. The first and second terminals are electrically coupled to first and second bus sections. First and second semiconductor devices between the terminals control current flow and there is a current connection from each terminal to a power switching assembly controller for providing an indication of current. A control signal line is connected between the power switching assembly controller and each semiconductor device provides a signal to the semiconductor devices to control the current flow and an inverter coupler couples each current connection to the inverter. The inverter coupler has a feed from each current connection to the inverter.

A circuit for regenerative gate charging includes an inductor coupled to a gate of a FET. An output control circuit is coupled to a timing control circuit and a bridged inductor driver, which is coupled to the inductor. A sense circuit is coupled to the gate and to the timing control circuit, which receives a control signal, generates output control signals in accordance with a first switch timing profile, and transmits the output control signals to the output control circuit. In accordance with the first switch timing profile, the output control circuit holds switches of the bridged inductor driver in an ON state for a first period and holds all of the switches in an OFF state for a second period. Gate voltages are sampled during the second period and after the first period. The timing control circuit generates a second switch timing profile using the sampled voltages.

A system includes an input port having an input voltage, an output port having an output voltage, and a power converter having a switch network with a plurality of power switches and a first resonant tank having a first resonant capacitor and a first resonant inductor, where at least one resonant component within the first resonant capacitor and the first resonant inductor is a switchable component configured to switch between different values. The system further includes a resonant mode selection block configured to adjust a value of the switchable component to maintain a performance of the system, and a controller configured to adjust a switching frequency or a duty cycle of the power converter.

A device to drive a plurality of power switches in a power converter with an input voltage port having an input voltage includes a drive resonant tank, a switch network, a control block configured to control the turn-on and turn-off of drive switches, and an output port. The drive resonant tank has a resonant inductor, and a resonant capacitor which includes an input capacitance of a power switch. The switch network has a plurality of drive switches, which are controlled such that the drive resonant tank goes through a resonant state and a pseudo clamp state consecutively during a switching period. A gate drive voltage of a power switch fluctuates slightly during the pseudo clamp state. The output port has two terminals coupled to a gate and a source of a power switch respectively.

In accordance with an embodiment, a method of controlling a switch driver includes energizing a first inductor in a first direction with a first energy; transferring the first energy from the first inductor to a second inductor, wherein the second inductor is coupled between a second switch-driving terminal of the switch driver and a second internal node, and the second inductor is magnetically coupled to the first inductor; asserting a first turn-on signal at the second switch-driving terminal using the transferred first energy; energizing the first inductor in a second direction opposite the first direction with a second energy after asserting the first turn-on signal at the second switch-driving terminal; transferring the second energy from the first inductor to the second inductor; and asserting a first turn-off signal at the second switch-driving terminal using the transferred second energy.

A circuit and method are provided for recuperating energy and decreasing driver power consumption in a switching converter. An inductor is directly connected between a gate driver and a gate electrode of a switch. A first burst pulse signal is generated, wherein energy from a power source is stored in the inductor and transferred to a parasitic capacitance of the switch. A driving pulse signal is subsequently generated to the gate electrode of the switch, wherein the gate voltage is equal to the supply voltage and no balancing current flows through the inductor. After the driving pulse signal is terminated a second burst pulse signal is generated, wherein energy is accumulated in the inductive element and returned to the power source. The energy provided from the power source during the first burst pulse signal is equal to the energy returned to the power source during the second burst pulse signal.

Described herein are reduced-power electronic circuits with wide-band energy recovery using non-interfering topologies. A resonant clock distribution network comprises a plurality of resonant clock drivers that receive at least one of a plurality of reference clock signals. An energy saving component is coupled with the plurality of resonant clock drivers. The energy saving component provides for lower energy consumption by resonating with unwanted parasitic capacitance of a load capacitance. The energy saving component and the load capacitance (LC) form a series resonant frequency that is significantly greater than a clock frequency of the plurality of resonant clock drivers, so that output clock signal paths are not interfered with and so that effects on skew are minimized.

Described herein are reduced-power electronic circuits with wide-band energy recovery using non-interfering topologies. A digital logic driver comprising a pulldown switch, an energy saving component (e.g., inductor) coupled in series with the pulldown switch, and a reference supply connected in series with the energy saving component that is configured to enable the digital logic driver to resonate with a load capacitance and reuse electrical energy at the load capacitance without interfering with a signal path of the digital logic driver.