A signal generator with direct digital synthesis and tacking filter to generate an oscillator signal. A digital signal generator generates a digital signal; a digital to analog converter is connected to an output of the digital signal generator and converts the digital signal to an analog signal; a filter is coupled to an output of the DAC and filters the analog signal and generates the oscillator signal; a comparator is coupled to an output of the filter and generates a signal indicating zero crossings of the filter output signal; a digital control unit is coupled to outputs of the digital signal generator and comparator and generates a control signal to tune the filter to track a center frequency of the generated oscillator signal. The control signal is generated based on adjacent samples values from the digital signal generator before and after zero crossings of the filter output signal.

Various embodiments relate to a free running oscillator, that includes a switch capacitor based frequency-to-voltage converter (F2V), a comparator, and a voltage controlled oscillator (VCO), which may be collectively configured to reduce amplifier offset and flicker noise while increasing effective gain of the amplifier of the comparator. The F2V may produce a feedback voltage Vfb corresponding to frequencies of output of the VCO. The comparator may be configured to sample a reference voltage Vref using a sampling capacitor, compare Vref to Vfb, and generate an output based on any difference between Vref and Vfb, where the output may be integrated using an integrating capacitor of the comparator. The comparator may compensate for parasitic capacitance at the output of the amplifier by using an amplifier having two outputs, with the sampling capacitor and integrating capacitor being coupled to respectively different outputs of the amplifier.

A method for multiphase frequency to voltage conversion includes generating for each cycle of an oscillating input, one of a plurality of non-overlapping clocks. A respective voltage in proportion to an input frequency of the oscillating input, is generated in response to each of the non-overlapping clocks, with a respective one of a plurality of frequency to voltage converters. Each of the respective voltages is summated to generate a voltage sum proportional to the input frequency.

A phase-locked loop (PLL) may include a phase-frequency detector (PFD), a phase interpolation (PI)-based sampler, a loop filter, a voltage-controlled oscillator (VCO), and a fractional frequency divider. The PFD output corresponds to a phase error between a reference clock signal and a feedback signal. The PI-based sampler produces a slope signal in response to the PFD output, and adjusts the slope signal in response to a quantization error correction indication. The PI-based sampler also samples the slope signal. The loop filter produces a VCO control signal in response to a sampled slope signal. The VCO control signal controls the VCO frequency. The fractional frequency divider circuit divides the frequency of the VCO output signal and also determines the quantization error correction corresponding to the quantization error introduced by fractional division of the frequency of the VCO output signal.

A method for multiphase frequency to voltage conversion includes generating for each cycle of an oscillating input, one of a plurality of non-overlapping clocks. A respective voltage in proportion to an input frequency of the oscillating input, is generated in response to each of the non-overlapping clocks, with a respective one of a plurality of frequency to voltage converters. Each of the respective voltages is summated to generate a voltage sum proportional to the input frequency.

A method for multiphase frequency to voltage conversion includes generating for each cycle of an oscillating input, one of a plurality of non-overlapping clocks. A respective voltage in proportion to an input frequency of the oscillating input, is generated in response to each of the non-overlapping clocks, with a respective one of a plurality of frequency to voltage converters. Each of the respective voltages is summated to generate a voltage sum proportional to the input frequency.

A self-oscillating spread spectrum frequency control loop contains a gated voltage-controlled oscillator (VCO) which receives a digital signal that can start or stop its oscillation. The VCO generates a spread spectrum carrier by receiving a triangle wave signal from a delaying ramp generator in a loop, its ramp direction controlled by a frequency comparator. The loop generates a spectrum spread as wide as possible above a minimum frequency. RF isolators that utilize low-pass filters in the transmitter and high-pass filters in the receiver, where the F-3 dB cutoff frequencies of both filters vary in a correlated manner, are used to not produce spread spectrum frequencies below the minimum frequency. Die from a given wafer lot, when designed such that the low- and high-pass cutoff frequencies track, can be used to form RF digital isolators whose minimum spread spectrum frequency does not go below the minimum frequency required by that wafer lot.

A semiconductor device includes a clock generator which receives an input clock and generates an output clock, a reference voltage generator which receives the input clock or the output clock, generates a sub-reference voltage in accordance with a frequency of the input clock or a frequency of the output clock, and generates a reference voltage using the sub-reference voltage and a preset error voltage, and a clock detector which receives the output clock, generates a first output voltage in accordance with the output clock, and compares the generated first output voltage with the reference voltage to output an error signal based on the output clock, wherein the preset error voltage is set in accordance with a degree of preset error of the output clock.

A high voltage generating circuitry includes a charge-pump and control loop; the control loop includes a voltage divider which receives a high voltage and provides a divided high voltage output. A first circuit element provides a first voltage difference signal. A controller generates a feedback signal based on the first voltage difference signal. An oscillator generates clock signals for operating the charge-pump circuitry, with the frequency of the clock signals being controlled with a control signal. A feedforward path with a second circuit element combines a second reference voltage and a second voltage generated by inverting the supply voltage for obtaining a second voltage difference signal. A third circuit element generates a feedforward compensation signal inversely proportional to a voltage difference between the supply voltage and the second reference voltage. A fourth circuit element generates the control signal by summing the feedback signal and the feedforward compensation signal.

An oscillator circuit arrangement comprises a gain stage and a feedback loop that includes a crystal device. A clock signal monitor circuit is connected to an output of the gain stage and detects a frequency shift in the clock signal or a loss of oscillation. The current through the gain stage is controlled in response to a control signal generated by the clock signal monitor circuit.