H03L7/02

Relaxation Oscillator and Method for Operating a Relaxation Oscillator
20200162059 · 2020-05-21 ·

A method of operating a relaxation oscillator includes determining a measure of a propagation delay of a detection device of a relaxation oscillator and increasing a charging rate of a capacitor device of the relaxation oscillator for a time duration based on the determined measure of the propagation delay.

Digitally reconfigurable ultra-high precision internal oscillator
10581438 · 2020-03-03 · ·

A system, method and apparatus for tuning an internal oscillator to a desired frequency F1 is shown and uses an RC delay element that comprises a resistor, a capacitor and a comparator. The method includes receiving a clock signal from an oscillator to be tuned, triggering charging of the RC delay element, and N clock cycles after triggering the charging, the method determines whether the charge on the precision RC delay element is higher than or lower than a reference voltage. Correction to the clock frequency is based on the results.

Digitally reconfigurable ultra-high precision internal oscillator
10581438 · 2020-03-03 · ·

A system, method and apparatus for tuning an internal oscillator to a desired frequency F1 is shown and uses an RC delay element that comprises a resistor, a capacitor and a comparator. The method includes receiving a clock signal from an oscillator to be tuned, triggering charging of the RC delay element, and N clock cycles after triggering the charging, the method determines whether the charge on the precision RC delay element is higher than or lower than a reference voltage. Correction to the clock frequency is based on the results.

Digital downconverter with digital oscillator frequency error correction

A digital local oscillator includes a look-up table and oscillator control circuitry. The look-up table contains samples of the digital local oscillator signal. The oscillator control circuitry is configured to select samples from the look-up table based on an accumulated phase value. The oscillator control circuitry is also configured to add a correction value to the accumulated phase value based on a difference of a frequency of the digital local oscillator signal and a desired frequency.

Digital downconverter with digital oscillator frequency error correction

A digital local oscillator includes a look-up table and oscillator control circuitry. The look-up table contains samples of the digital local oscillator signal. The oscillator control circuitry is configured to select samples from the look-up table based on an accumulated phase value. The oscillator control circuitry is also configured to add a correction value to the accumulated phase value based on a difference of a frequency of the digital local oscillator signal and a desired frequency.

Systems and methods for storing frequency information for system calibration/trimming

Embodiments of the present disclosure include a microcontroller with a frequency test circuit, a device-under-test (DUT) input, and a calculation engine circuit. The calculation engine circuit is configured to compare a measured frequency from the frequency test circuit measured from the DUT input to a reference frequency stored in memory, and, based on the comparison, adjust frequency of the DUT generating the DUT input.

Systems and methods for storing frequency information for system calibration/trimming

Embodiments of the present disclosure include a microcontroller with a frequency test circuit, a device-under-test (DUT) input, and a calculation engine circuit. The calculation engine circuit is configured to compare a measured frequency from the frequency test circuit measured from the DUT input to a reference frequency stored in memory, and, based on the comparison, adjust frequency of the DUT generating the DUT input.

Closed-loop control device with adaptive fault compensation

A closed-loop control device to control a system to be controlled includes a front node, back node, external tapping point, controller and compensating circuit. The compensating circuit has an inner node, frequency filter, front buffer and back buffer. The front node determines a difference; the back node supplies an external sum signal. A setting device automatically suppresses use of the output signal of the front buffer, supplies the back buffer and the back node with a first excitation signal as the compensation signal and detects a first result signal produced by the first excitation signal. The first result signal is one of the control difference, internal sum signal, output filtered signal of the frequency filter or output signal of the front buffer. The setting device evaluates the first excitation signal and the first result signal, sets a parameter of the frequency filter and the second propagation delay.

Closed-loop control device with adaptive fault compensation

A closed-loop control device to control a system to be controlled includes a front node, back node, external tapping point, controller and compensating circuit. The compensating circuit has an inner node, frequency filter, front buffer and back buffer. The front node determines a difference; the back node supplies an external sum signal. A setting device automatically suppresses use of the output signal of the front buffer, supplies the back buffer and the back node with a first excitation signal as the compensation signal and detects a first result signal produced by the first excitation signal. The first result signal is one of the control difference, internal sum signal, output filtered signal of the frequency filter or output signal of the front buffer. The setting device evaluates the first excitation signal and the first result signal, sets a parameter of the frequency filter and the second propagation delay.

Oscillator using supply regulation loop and operating method thereof

An oscillator using a supply regulation loop and a method of operating the oscillator are provided. The oscillator includes a reference voltage generator configured to generate reference voltages from a supply voltage, a supply regulation loop circuit including a first operational amplifier and a transistor, the first operational amplifier being configured to receive a first reference voltage of the reference voltages, and the transistor being connected to an output terminal of the first operational amplifier, and a frequency locked loop (FLL) circuit configured to generate a clock signal, based on an input voltage determined based on a current flowing in the transistor and a second reference voltage of the reference voltages, wherein the first operational amplifier may include an input terminal configured to receive the first reference voltage and to receive negative feedback from the transistor, and the output terminal being configured to generate an output voltage independent of noise of the supply voltage.