A system for tracking a received signal with a subcarrier, the received signal representing a carrier signal modulated with a code signal and with a subcarrier signal. The system comprises independent and cooperatively operating loops: a phase lock loop tracking the carrier signal, a subcarrier lock loop tracking the subcarrier signal, and a delay lock loop tracking the code signal. The subcarrier lock loop comprises a first controllable oscillator and a first early-minus-late discriminator generating a control signal for the first controllable oscillator. The delay lock loop comprising a second controllable oscillator and a second arctan discriminator generating a control signal for the second controllable oscillator.

A system, method and apparatus for tuning an internal oscillator to a desired frequency F1 is shown and uses an RC delay element that comprises a resistor, a capacitor and a comparator. The method includes receiving a clock signal from an oscillator to be tuned, triggering charging of the RC delay element, and N clock cycles after triggering the charging, the method determines whether the charge on the precision RC delay element is higher than or lower than a reference voltage. Correction to the clock frequency is based on the results.

Digital control of a crystal oscillator is implemented in a manner that allows frequency accuracy to be traded off dynamically with power consumption. The oscillator transitions between a less accurate/lower power mode and a high accuracy/higher power mode smoothly without requiring any external clock source during the transition. Power consumption is optimized because the crystal oscillator provides the clock source during transitions between the power modes and no other clock source is needed for these transitions. The system can also optimize the startup time and steady state power consumption independently.

Digital control of a crystal oscillator is implemented in a manner that allows frequency accuracy to be traded off dynamically with power consumption. The oscillator transitions between a less accurate/lower power mode and a high accuracy/higher power mode smoothly without requiring any external clock source during the transition. Power consumption is optimized because the crystal oscillator provides the clock source during transitions between the power modes and no other clock source is needed for these transitions. The system can also optimize the startup time and steady state power consumption independently.

A micro electro mechanical system (MEMS) oscillator supplies an oscillator output signal having a first frequency that differs from a predetermined frequency of the output signal. An error determination circuit determines frequency error from the predetermined frequency based on initial frequency offset and/or temperature and provides the error information indicating a difference between the first frequency and the predetermined frequency. The error information is used by a receiving system in frequency translation logic that utilizes the oscillator output signal as a frequency reference.

An asynchronous digital logic is used to provide a pulse. A pulse train is filtered to determine an analog measurement based at least in part on the duty cycle of the pulse. The analog measurement is compared with a tunable reference associated with a programmable locked delay for the DLL. A digital code is sequenced based at least in part on the comparison. A digitally controlled delay line is programmed based at least in part on the digital code.

An asynchronous digital logic is used to provide a pulse. A pulse train is filtered to determine an analog measurement based at least in part on the duty cycle of the pulse. The analog measurement is compared with a tunable reference associated with a programmable locked delay for the DLL. A digital code is sequenced based at least in part on the comparison. A digitally controlled delay line is programmed based at least in part on the digital code.

A system for tracking a received signal with a subcarrier, the received signal representing a carrier signal modulated with a code signal and with a subcarrier signal. The system comprises independent and cooperatively operating loops: a phase lock loop tracking the carrier signal, a subcarrier lock loop tracking the subcarrier signal, and a delay lock loop tracking the code signal. The subcarrier lock loop comprises a first controllable oscillator and a first early-minus-late discriminator generating a control signal for the first controllable oscillator. The delay lock loop comprising a second controllable oscillator and a second arctan discriminator generating a control signal for the second controllable oscillator.

A frequency locked loop circuit, comprising an operational circuit, a first impedance circuit, a second impedance circuit, a switching circuit and a frequency generation circuit. The operational circuit is configured to output an operational signal according to a voltage difference between a positive terminal and a negative terminal. The switching circuit is configured to periodically conduct the negative terminal to one of the first impedance node and the second impedance node, and periodically conduct the positive terminal to the other one of the first impedance node and the second impedance node. The frequency generation circuit is configured to periodically sample the operational signal to generate a sample signal to generate a clock signal. An operational frequency of the operational signal is an integer multiple of a sampling frequency of the frequency generation circuit.

A self-biased, closed loop, low current free running oscillator clock generator method and apparatus are provided with a current mode comparator connected to a trimming resistor and configured to compare an internally generated voltage reference V.sub.REF signal to a voltage feedback signal V.sub.FB, where the current mode comparator comprises a common gate amplifier connected to a current mirror circuit in a negative self-biased closed loop to generate a control current signal for controlling a current controlled oscillator to produce an output clock signal having a clock frequency based on the control current signal, where a frequency-to-voltage converter is connected in a feedback path to receive the output clock signal and is configured to produce the voltage feedback signal V.sub.FB for input to the current mode comparator, wherein the clock frequency of the output clock signal is tuned to a nominal locked output frequency f.sub.OUT by the trimming resistor.