The invention concerns an apparatus comprising an analog circuit and a digital circuit. The analog circuit may be configured to generate an enable signal in response to (i) a comparison of a width of an up pulse and a pre-determined width and (ii) a comparison of a width of a down pulse and the pre-determined width. The up pulse and the down pulse may be generated in response to a comparison of a feedback signal and a reference signal. The enable signal may be active when both the comparisons are within a pre-determined threshold. The digital circuit may be configured to generate an output signal representing a lock status between (i) the feedback signal and (ii) the reference signal. The lock status may be determined (a) during a decision window based on a number of pulses of the reference signal and (b) when the enable signal is active.

An oscillator circuit includes an oscillating circuit coupled to a vibrator, and a control circuit that controls the oscillating circuit. The oscillator circuit has a normal operation mode in which the oscillating circuit oscillates in a state where a negative resistance value is a first value, and a start mode in which the oscillator circuit shifts from a state where oscillation is stopped to the normal operation mode. In the start mode, the control circuit controls the negative resistance value to increase from a second value which is smaller than the first value.

An oscillator circuit includes an oscillating circuit coupled to a vibrator, and a control circuit that controls the oscillating circuit. The oscillator circuit has a normal operation mode in which the oscillating circuit oscillates in a state where a negative resistance value is a first value, and a start mode in which the oscillator circuit shifts from a state where oscillation is stopped to the normal operation mode. In the start mode, the control circuit controls the negative resistance value to increase from a second value which is smaller than the first value.

A spread spectrum clock generator includes a phase comparator that compares a reference clock with a feedback clock, a low-pass filter that passes a predetermined low-frequency component, a phase lock loop that includes a voltage-controlled oscillator generating an output clock whose frequency corresponds to the filtered signal, a triangular wave controller that generates a triangular wave signal for frequency-modulating the spread spectrum clock based on the output clock, a delay controller that generates the feedback clock by controlling delay of the output clock based on the triangular wave signal, a first counter that counts the output clock and output a first count value, a second counter that counts the reference clock and output a second count value, and a phase error correction circuit that compares the first count value with the second count value and corrects phase error of the output clock.

A circuit includes a period calculator and a pulse width calculator. The period calculator is configured for receiving a first predetermined digital code and a second predetermined digital code, and for calculating a first calculated period value according to the first predetermined digital code, and calculating a second calculated period value according to the second predetermined digital code. The first predetermined digital code has a first predetermined period value, and the second predetermined digital code has a second predetermined period value. The pulse width calculator is configured for receiving a predetermined pulse width, and calculating a first pulse width code corresponding to the predetermined pulse width according to the first predetermined period value, the second predetermined period value, the first calculated period value, the second calculated period value and the predetermined pulse width.

A circuit includes a period calculator and a pulse width calculator. The period calculator is configured for receiving a first predetermined digital code and a second predetermined digital code, and for calculating a first calculated period value according to the first predetermined digital code, and calculating a second calculated period value according to the second predetermined digital code. The first predetermined digital code has a first predetermined period value, and the second predetermined digital code has a second predetermined period value. The pulse width calculator is configured for receiving a predetermined pulse width, and calculating a first pulse width code corresponding to the predetermined pulse width according to the first predetermined period value, the second predetermined period value, the first calculated period value, the second calculated period value and the predetermined pulse width.

A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.

A phase locked loop circuit that is capable of stabilizing a frequency of an input signal even in the case where the frequency is unstable is provided. The phase locked loop circuit 12 that corrects a frequency error of an output signal from an oscillator to a predetermined target frequency; an ADC 121 that converts the output signal to a digital signal; reference frequency output means 123 that outputs a reference frequency signal; frequency error detection means 122a that detects the frequency error based on the digital signal and the reference frequency signal; correction signal generation means 122b that generates an error correction signal based on the frequency error; a DAC 124 that converts the error correction signal to an analog signal; and a multiplier 125 that multiplies the output signal by the analog signal to correct the frequency error of the output signal.

A method and system are disclosed for measuring a specified parameter in a phase-locked loop frequency synthesizer (PLL). In one embodiment, the method comprises introducing multiple phase errors in the PLL, measuring a specified aspect of the introduced phase errors, and determining a value for the specified parameter using the measured aspects of the introduced phase errors. In one embodiment, the phase errors are introduced repetitively in the PLL, and these phase errors produce a modified phase difference between the reference signal and the feedback signal in the PPL. In one embodiment, crossover times, when this modified phase difference crosses over a preset value, are determined, and these crossover times are used to determine the value for the specified parameter. In an embodiment, the parameter is calculated as a mathematical function of the crossover times. The parameter may be, for example, the bandwidth of the PLL.

Provided are a digitally controlled oscillator and an electronic device including the digitally controlled oscillator. The digitally controlled oscillator includes a digital control unit and a power control oscillation unit. The digital control unit compensates for a difference between a feedback signal of an output power and a reference power set based on an input digital control signal and outputting an output power. The power control oscillation unit receives a signal related to the output power, and generates an output clock having an oscillation frequency in response to the signal related to the output power.