Embodiments of an integrated circuit (IC) comprising circuitry to determine settings for an injection-locked oscillator (ILO) are described. In some embodiments, an injection signal is generated based on a first clock edge of a reference clock signal, and is injected into an ILO. Next, one or more output signals of the ILO are sampled based on a second clock edge of the reference clock signal, and settings for the ILO are determined based on the samples. In some embodiments, a sequence of two or more time-to-digital (TDC) codes is generated based on a reference clock signal and a free-running ILO. In some embodiments, the TDC circuitry that is already present in a delay-locked loop is reused for determining the sequence of two or more TDC codes. The ILO settings can then be determined based on the sequence of two or more TDC codes.

Embodiments of an integrated circuit (IC) comprising circuitry to determine settings for an injection-locked oscillator (ILO) are described. In some embodiments, an injection signal is generated based on a first clock edge of a reference clock signal, and is injected into an ILO. Next, one or more output signals of the ILO are sampled based on a second clock edge of the reference clock signal, and settings for the ILO are determined based on the samples. In some embodiments, a sequence of two or more time-to-digital (TDC) codes is generated based on a reference clock signal and a free-running ILO. In some embodiments, the TDC circuitry that is already present in a delay-locked loop is reused for determining the sequence of two or more TDC codes. The ILO settings can then be determined based on the sequence of two or more TDC codes.

In one embodiment, a local clock is synchronized to a master clock using a Kalman filter to determine state variables using a state transition matrix that includes at least one coefficient that is associated with a digital-to-analog converter (DAC), where the state variables include a unit step variable indicative of a unit step for the system. The local clock is controlled based on the state variables determined using the Kalman filter. The unit step is indicative of an amount by which the frequency of the local clock signal changes in response to a change in the digital input of the DAC.

In one embodiment, a local clock is synchronized to a master clock using a Kalman filter to determine state variables using a state transition matrix that includes at least one coefficient that is associated with a digital-to-analog converter (DAC), where the state variables include a unit step variable indicative of a unit step for the system. The local clock is controlled based on the state variables determined using the Kalman filter. The unit step is indicative of an amount by which the frequency of the local clock signal changes in response to a change in the digital input of the DAC.

A variable phase generator is disclosed that includes a delay line with an input, and output, and a delay lone control signal input. A signal on the delay line output has a phase offset relative to the delay line input signal such that the phase offset is controlled by a digital offset signal. A phase detector process the input signal and the output signal to generate a phase detector output signal. A charge pump, responsive to the phase detector output signal, generates a charge pump output. A digital to analog converter receives and converts the digital offset signal to an analog offset signal. A control node is connected to the delay line control input, the charge pump, and the digital to analog converter, and is configured to receive and combine the charge pump output and the analog offset signal to create the delay line control signal.

A semiconductor system may include a first semiconductor device configured to output a clock, receive and output data, and detect a jitter of a transmission path according to a level combination of a plurality of monitoring signals. The semiconductor system may also include a second semiconductor device configured to generate the plurality of monitoring signals of which the level combination is changed according to phase differences between an internal clock generated through the transmission path for transmitting the clock and a plurality of divided clocks obtained by dividing the frequency of the clock.

A semiconductor system may include a first semiconductor device configured to output a clock, receive and output data, and detect a jitter of a transmission path according to a level combination of a plurality of monitoring signals. The semiconductor system may also include a second semiconductor device configured to generate the plurality of monitoring signals of which the level combination is changed according to phase differences between an internal clock generated through the transmission path for transmitting the clock and a plurality of divided clocks obtained by dividing the frequency of the clock.

A frequency estimator for estimating a frequency, including a counter configured to count an integer number of full clock cycles during a measurement time window; a Time-to-Digital Converter (TDC) configured to measure a fraction of a clock cycle during the measurement time window; and a processor configured to determine the estimated frequency based on the counted number of full clock cycles and the measured fraction of the clock cycle.

A phase-locked loop circuit comprises a multi-phase oscillator having a plurality of coupled oscillators. A calibration module detects mismatches between frequency characteristics of the different oscillators in the phase-locked loop circuit during a calibration process. The calibration module then calibrates the various oscillators to compensate for the detected mismatch. Once calibrated, the phase-locked loop circuit can operate with little or no performance degradation despite the mismatch in frequency characteristics between the different oscillators.

A phase-locked loop circuit comprises a multi-phase oscillator having a plurality of coupled oscillators. A calibration module detects mismatches between frequency characteristics of the different oscillators in the phase-locked loop circuit during a calibration process. The calibration module then calibrates the various oscillators to compensate for the detected mismatch. Once calibrated, the phase-locked loop circuit can operate with little or no performance degradation despite the mismatch in frequency characteristics between the different oscillators.