A source-synchronous clocking signal is sampled by an edge sampler triggered by a phase-adjusted version of the clocking signal. The output of the edge sampler is used as a phase-error indicator for a filtered feedback loop that aligns the phase-adjusted clocking signal to minimize, on average, the difference between the received source-synchronous clocking signal and the phase-adjusted version of the clocking signal minus the setup time of the sampler. This forms a delay-locked loop configuration. The phase adjustment information used to produce the aligned phase-adjusted clocking signal is then to produce a receiver clocking signal that is used to sample the source-synchronous data signal.

A source-synchronous clocking signal is sampled by an edge sampler triggered by a phase-adjusted version of the clocking signal. The output of the edge sampler is used as a phase-error indicator for a filtered feedback loop that aligns the phase-adjusted clocking signal to minimize, on average, the difference between the received source-synchronous clocking signal and the phase-adjusted version of the clocking signal minus the setup time of the sampler. This forms a delay-locked loop configuration. The phase adjustment information used to produce the aligned phase-adjusted clocking signal is then to produce a receiver clocking signal that is used to sample the source-synchronous data signal.

A signal recovery circuit includes a clock code generation circuit configured to generate codes in response to an enable signal and a clock, and a pulse recovery circuit configured to generate an output pulse in response to an input pulse and the codes.

A signal recovery circuit includes a clock code generation circuit configured to generate codes in response to an enable signal and a clock, and a pulse recovery circuit configured to generate an output pulse in response to an input pulse and the codes.

Described are apparatus and methods for high frequency clock generation. A circuit includes a phase frequency detector (PFD) which outputs differential error clocks based on comparison of differential reference clocks and differential feedback clocks, which are at a first frequency. A controlled oscillator (CO) connected to the PFD, which adjusts a frequency of the CO based on the differential error clocks to generate differential clocks at a second frequency, which is a multiple of the first frequency. A quadrature clock generator connected to the CO, which generates differential quadrature clocks at the second frequency from the differential clocks, where the differential feedback clocks are generated from the differential clocks and one pair of the differential quadrature clocks. A frequency doubler which doubles each pair of the differential quadrature clocks and outputs fully differential and balanced clocks at a third frequency for distribution, which is a multiple of the second frequency.

In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.

In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.

Embodiments of an integrated circuit (IC) comprising circuitry to determine settings for an injection-locked oscillator (ILO) are described. In some embodiments, an injection signal is generated based on a first clock edge of a reference clock signal, and is injected into an ILO. Next, one or more output signals of the ILO are sampled based on a second clock edge of the reference clock signal, and settings for the ILO are determined based on the samples. In some embodiments, a sequence of two or more time-to-digital (TDC) codes is generated based on a reference clock signal and a free-running ILO. In some embodiments, the TDC circuitry that is already present in a delay-locked loop is reused for determining the sequence of two or more TDC codes. The ILO settings can then be determined based on the sequence of two or more TDC codes.

Embodiments of an integrated circuit (IC) comprising circuitry to determine settings for an injection-locked oscillator (ILO) are described. In some embodiments, an injection signal is generated based on a first clock edge of a reference clock signal, and is injected into an ILO. Next, one or more output signals of the ILO are sampled based on a second clock edge of the reference clock signal, and settings for the ILO are determined based on the samples. In some embodiments, a sequence of two or more time-to-digital (TDC) codes is generated based on a reference clock signal and a free-running ILO. In some embodiments, the TDC circuitry that is already present in a delay-locked loop is reused for determining the sequence of two or more TDC codes. The ILO settings can then be determined based on the sequence of two or more TDC codes.

A signal distribution system includes: a first signal divider arranged to generate a first output oscillating signal according to a first input oscillating signal; a second signal divider arranged to generate a second output oscillating signal according to the first input oscillating signal; a first transmitting channel coupled to the first signal divider and the second divider for transmitting the first input oscillating signal to the first signal divider and the second signal divider; and a second transmitting channel coupled to the first signal divider and the second divider for transmitting a second input oscillating signal to the first signal divider and the second signal divider; wherein the first input oscillating signal has a first frequency, the second input oscillating signal has a second frequency, and the second frequency is smaller than the first frequency.