According to a clock generator, an oscillator outputs source oscillation clocks which are trimmed according to a trimming code. A first frequency divider generates X frequency division clocks by frequency-dividing the source oscillation clocks by a first frequency division ratio X. A trimming controller changes the trimming code within a period of the X frequency division clocks and supplies the changed trimming code to the oscillator.

According to a clock generator, an oscillator outputs source oscillation clocks which are trimmed according to a trimming code. A first frequency divider generates X frequency division clocks by frequency-dividing the source oscillation clocks by a first frequency division ratio X. A trimming controller changes the trimming code within a period of the X frequency division clocks and supplies the changed trimming code to the oscillator.

An electronic device includes: a first input node configured to receive a dock signal; a second input node configured to receive an activation signal or a deactivation signal; a filter circuit responsive to: (a) the activation signal to activate the filter circuit to block the dock signal; or (b) the deactivation signal to deactivate the filter circuit to pass the dock signal; and an output node configured for coupling to a synchronous I/O interface of an integrated circuit to control operation of the synchronous I/O interface.

An electronic device includes: a first input node configured to receive a dock signal; a second input node configured to receive an activation signal or a deactivation signal; a filter circuit responsive to: (a) the activation signal to activate the filter circuit to block the dock signal; or (b) the deactivation signal to deactivate the filter circuit to pass the dock signal; and an output node configured for coupling to a synchronous I/O interface of an integrated circuit to control operation of the synchronous I/O interface.

A circuit for facilitating random edge injection locking of an oscillator comprises a clock signal and a digitally controlled delay line, where the digitally controlled delay line is configured to delay the clock signal, thereby generating a delayed clock signal. The circuit further comprises an edge selector configured to generate a phase select signal with a random pulse sequence. Moreover, the circuit comprises a pulse generator downstream to the digitally controlled delay line configured to generate injection pulses from the delayed clock signal for at least two phases of the oscillator based on the phase select signal.

Clock generation circuitry includes quadrature locked loop circuitry having first injection locked oscillator circuitry, second injection locked oscillator circuitry, and XOR circuitry. The first injection locked oscillator circuitry receives a first input signal and a second input signal and outputs first clock signals. The first input signal and the second input signal correspond to a reference clock signal. The second injection locked oscillator circuitry is coupled to outputs of the first injection locked oscillator circuitry, and receives the first clock signals and generates second clock signals. The XOR circuitry receives the second clock signals and generates a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal. The frequencies of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are greater than the frequency of the reference clock signal.

A bandpass filter configured to receive a temporally modulated periodic input signal Vin(t), and to deliver an output signal Vout(t), and includes, in combination: a phase comparator configured to receive, on a first input, the temporally modulated periodic input signal Vin(t) as first signal, and to generate an output signal with a variable duty cycle; coupled to an injection-locked oscillator configured to receive as input, the output signal from the phase comparator, and to generate a signal Vr(t) that is phase-offset with respect to the output signal from the phase comparator; the phase-offset signal being applied to a second input of the phase comparator as second input signal; and the output signal from the phase comparator being the output signal Vout(t) from the bandpass filter and being representative of the phase difference between the two input signals Vin(t) and Vr(t).

A bandpass filter configured to receive a temporally modulated periodic input signal Vin(t), and to deliver an output signal Vout(t), and includes, in combination: a phase comparator configured to receive, on a first input, the temporally modulated periodic input signal Vin(t) as first signal, and to generate an output signal with a variable duty cycle; coupled to an injection-locked oscillator configured to receive as input, the output signal from the phase comparator, and to generate a signal Vr(t) that is phase-offset with respect to the output signal from the phase comparator; the phase-offset signal being applied to a second input of the phase comparator as second input signal; and the output signal from the phase comparator being the output signal Vout(t) from the bandpass filter and being representative of the phase difference between the two input signals Vin(t) and Vr(t).

A phase-tracking self-injection-locked (SIL) radar includes an SIL oscillator, a phase-tracking SIL loop and a frequency-locked loop. The SIL oscillator generates an electrical oscillation signal and receives an electrical injection signal related to the electrical oscillation signal for self-injection locking. The phase-tracking SIL loop receives the electrical oscillation signal and outputs the electrical injection signal to the SIL oscillator with a constant phase difference between the electrical oscillation signal and the electrical injection signal. The frequency-locked loop receives the electrical oscillation signal and produces an electrical control signal to control the phase-tracking SIL loop or the SIL oscillator for eliminating the frequency shift of the SIL oscillator caused by the phase-tracking SIL loop. Accordingly, the phase difference between the electrical oscillation signal and the electrical injection signal is maintained at 0° or 180° such that the phase-tracking SIL radar operates at optimal detection points.

A method of manufacturing an oscillator including housing a first resonator and a first integrated circuit device configured to oscillate the first resonator in a first container to manufacture the first oscillator, and housing a second resonator and a second integrated circuit device configured to oscillate the second resonator in a second container to manufacture the second oscillator, wherein the first integrated circuit device includes a first oscillation circuit configured to oscillate the first resonator to output a first oscillation signal, and no PLL circuit, the second integrated circuit device includes a second oscillation circuit configured to oscillate the second resonator to output a second oscillation signal, and a PLL circuit to which the second oscillation signal is input, and which is configured to output a third oscillation signal, and the first container and the second container are containers same in type.