Patent classifications
H03L2207/05
Apparatus and method for automatic search of sub-sampling phase locked loop (SS-PLL) locking acquisition
An apparatus and method are provided. The apparatus includes a phase locked loop (PLL) configured to generate a reference signal; a sub-sampling PLL (SS-PLL) connected to the PLL and configured to sub-sample the reference signal; and a first pre-charge circuit connected to the SS-PLL and configured to allow an output voltage of the SS-PLL to transition to an operating voltage to indicate that a difference between two voltage inputs is zero on average.
APPARATUS AND METHOD FOR AUTOMATIC SEARCH OF SUB-SAMPLING PHASE LOCKED LOOP (SS-PLL) LOCKING ACQUISITION
An apparatus and method are provided. The apparatus includes a phase locked loop (PLL) configured to generate a reference signal; a sub-sampling PLL (SS-PLL) connected to the PLL and configured to sub-sample the reference signal; and a first pre-charge circuit connected to the SS-PLL and configured to allow an output voltage of the SS-PLL to transition to an operating voltage to indicate that a difference between two voltage inputs is zero on average.
Frequency Sweep Generator and Method
An oscillator is configured to generate a signal with a frequency sweep, the oscillator having circuitry comprising a set of capacitors, each capacitor of the set of capacitors being switchably connectable in parallel in the circuitry so that the frequency of the signal has an intrinsic dependence on the number of the capacitors connected, a shift register controllable by a clock line and comprising a number of bits, each bit of the number of bits controlling connection of a respective capacitor of the set of capacitors so that the capacitors are connectable or disconnectable in a pre-determined order by shifting, respectively, activation or de-activation bits into the shift register, wherein the shifting is paced by the clock line; and a clock signal generator configured to output a clock signal with a time modulation on the clock line.
Adaptive voltage frequency scaling for optimal power efficiency
Aspects of the present invention are directed to techniques for improving the efficiency of power supply schemes by continuously and adaptively scaling voltage and frequency levels in an integrated circuit based on measured conditions in real-time, without resorting to a reliance on excessive pre-computed margins typical of conventional schemes. Embodiments of the present invention employ a self-tuning dynamic voltage control oscillator (or other similar clock signal generator) that sets the frequency for components in the integrated circuit. When a requested frequency exceeds a maximum allowed frequency for a given voltage level (accounting for other age and temperature related conditions), a look-up table is dynamically referenced to determine a new voltage level that is sufficient to safely and efficiently generate the requested frequency. The look-up table continuously receives updates on the operating conditions, and new voltage requests can be generated dynamically as necessary based on the system's current needs.
Calibration of a voltage controlled oscillator to trim the gain thereof, using a phase locked loop and a frequency locked loop
Disclosed herein is a method of calibrating a voltage controlled oscillator (VCO) for a phase locked loop. The method includes prior to activating the phase locked loop, and prior to activating a frequency locked loop, causing a bias signal generator circuit to generate a control signal with a fixed control voltage for the VCO. The method continued with activating the frequency locked loop, and adjusting the bias signal generator to calibrate a transconductance of the bias signal generator while the frequency locked loop is activated. The frequency locked loop is then deactivated, and the phase locked loop is activated.
Voltage-controlled oscillator and phase locked loop circuit with such voltage-controlled oscillator
According to an embodiment, a voltage-controlled oscillator has a variable capacitive element with a capacitance that is changed by a voltage to be applied thereto. One electrode of the variable capacitive element is connected to a control input terminal where a control voltage that controls an oscillation frequency is applied thereto. It has a compensation voltage generation circuit that generates a voltage that changes with a temperature thereof. It has a resistive element with one end that is directly connected to another electrode of the variable capacitive element and another end that is supplied with an output voltage of the compensation voltage generation circuit.
CALIBRATION OF A VOLTAGE CONTROLLED OSCILLATOR TO TRIM THE GAIN THEREOF, USING A PHASE LOCKED LOOP AND A FREQUENCY LOCKED LOOP
Disclosed herein is a method of calibrating a voltage controlled oscillator (VCO) for a phase locked loop. The method includes prior to activating the phase locked loop, and prior to activating a frequency locked loop, causing a bias signal generator circuit to generate a control signal with a fixed control voltage for the VCO. The method continued with activating the frequency locked loop, and adjusting the bias signal generator to calibrate a transconductance of the bias signal generator while the frequency locked loop is activated. The frequency locked loop is then deactivated, and the phase locked loop is activated.
Frequency/phase synthesizer noise cancellation
An open-loop feed-forward cross-correlator noise cancellation device includes a synthesizer to generate a synthesized output clock signal based on a reference clock signal. The open-loop feed-forward cross-correlator noise cancellation device also includes a cross-correlator device coupled to the synthesizer to receive the reference clock signal and the synthesized output clock signal and to cross-correlate the reference clock signal and the synthesized output clock signal to generate a cross-correlated output signal. The open-loop feed-forward cross-correlator noise cancellation device further includes a signal control delay line coupled to the cross-correlator device to generate an anti-phase noise signal based on the cross-correlated output signal to counter uncorrelated phase noise from additional circuitry of the synthesizer.
FREQUENCY/PHASE SYNTHESIZER NOISE CANCELLATION
An open-loop feed-forward cross-correlator noise cancellation device includes a synthesizer to generate a synthesized output clock signal based on a reference clock signal. The open-loop feed-forward cross-correlator noise cancellation device also includes a cross-correlator device coupled to the synthesizer to receive the reference clock signal and the synthesized output clock signal and to cross-correlate the reference clock signal and the synthesized output clock signal to generate a cross-correlated output signal. The open-loop feed-forward cross-correlator noise cancellation device further includes a signal control delay line coupled to the cross-correlator device to generate an anti-phase noise signal based on the cross-correlated output signal to counter uncorrelated phase noise from additional circuitry of the synthesizer.
VOLTAGE-CONTROLLED OSCILLATOR AND PHASE LOCKED LOOP CIRCUIT WITH SUCH VOLTAGE-CONTROLLED OSCILLATOR
According to an embodiment, a voltage-controlled oscillator has a variable capacitive element with a capacitance that is changed by a voltage to be applied thereto. One electrode of the variable capacitive element is connected to a control input terminal where a control voltage that controls an oscillation frequency is applied thereto. It has a compensation voltage generation circuit that generates a voltage that changes with a temperature thereof. It has a resistive element with one end that is directly connected to another electrode of the variable capacitive element and another end that is supplied with an output voltage of the compensation voltage generation circuit.