A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.

An analog PLL comprising: a VCO configured to provide a PLL output signal; a phase detector (PD) configured to receive a feedback signal from the VCO and a reference signal and wherein the PD provides a PD signal to a low pass filter (LPF), the LPF configured to filter of the PD signal and provide the filtered signal as a tuning voltage for the VCO; and a tracking loop configured to receive the tuning voltage and comprising at least a tracking loop comparator configured to provide a comparator output voltage based on a difference between the tuning voltage and a target voltage, wherein an output of the tracking loop provides a tracking voltage based on the comparator output voltage and wherein the frequency of the PLL output voltage is based on the tuning voltage and the tracking voltage.

A fast frequency hopping implementation in a phase lock loop (PLL) circuit achieves a PLL lock to a new frequency in a very short period of time. In one instant, frequency allocation at a transceiver is changed. In response, a local oscillator frequency hops to a new center frequency based on the changed frequency allocation. The hopping to the new center frequency is based on two-point modulation of a phase locked loop.

A method and system are disclosed for measuring a specified parameter in a phase-locked loop frequency synthesizer (PLL). In one embodiment, the method comprises introducing multiple phase errors in the PLL, measuring a specified aspect of the introduced phase errors, and determining a value for the specified parameter using the measured aspects of the introduced phase errors. In one embodiment, the phase errors are introduced repetitively in the PLL, and these phase errors produce a modified phase difference between the reference signal and the feedback signal in the PPL. In one embodiment, crossover times, when this modified phase difference crosses over a preset value, are determined, and these crossover times are used to determine the value for the specified parameter. In an embodiment, the parameter is calculated as a mathematical function of the crossover times. The parameter may be, for example, the bandwidth of the PLL.

The present invention is related to a clock generating device for generating an internal clock signal having a frequency correlated with a clock frequency of an external oscillator when the clock frequency of the external oscillator is not specified in advance. A clock generating device 105 comprises a memory 134 and a PLL circuit 120. The memory 134 is configured to store information about a frequency of an external clock signal generated by an external oscillator 200 at a predetermined timing. The PLL circuit 120 generates a second clock signal correlated with a first clock signal based on the information stored in the memory 134.

The phase-lock loop (PLL) can include a variable frequency oscillator adjustable to control the phase of the output signal; a primary control subsystem including a phase detector and a connection between the output signal and the phase detector, the phase detector generating a primary control signal to adjust the variable frequency oscillator; and a secondary control subsystem having an analog-to-digital converter and a digital-to-analog converter connected in series to receive the primary control signal and generate a secondary control signal also connected to independently adjust the variable frequency oscillator.

An oscillator circuit includes a current source, an oscillating section, a first capacitor, and a setting section. The current source is coupled to a connection node, and is configured to cause a current having a current value based on an input voltage to flow from a first power node to the connection node. The oscillating section is provided on a current path between the connection node and a second power node. The oscillating section is configured to oscillate at an oscillation frequency based on a current flowing through the current path. The first capacitor is provided between the connection node and the second power node. The first capacitor has a capacitance that varies in accordance with a voltage at the connection node. The setting section is configured to perform variation operation on the basis of the voltage at the connection node. The variation operation is operation of varying an impedance between the connection node and the second power node.

Generating a composite interpolated phase-error signal for clock phase adjustment of a local oscillator by forming a summation of weighted phase-error signals generated using a matrix of partial phase comparators, each of which compare a phase of the local oscillator with a corresponding phase of a reference clock.

A phase locked loop includes a signal receiver configured to generate a mixed signal based on the received signal and an oscillator signal, and a frequency control circuit configured to compare the mixed signal to a reference signal, and adjust the oscillator signal based on a result of the comparing.

Controllability of an oscillator circuit is improved. The oscillator circuit has inverters in odd-numbered stages. A circuit is electrically connected to a power supply node of the inverters to which a high power supply potential is input. The circuit includes a first transistor, a second transistor, and a capacitor. The first transistor includes an oxide semiconductor in its channel. A holding circuit including the first transistor and the capacitor has a function of holding an analog potential that is input from the outside. The potential held by the holding circuit is input to a gate of the second transistor. A power supply potential is supplied to the inverters through the second transistor, so that the delay time of the inverter can be controlled by the potential of the gate of the second transistor.