In one aspect, a method includes: determining a power mode of a device; setting a first reference voltage level and a second reference voltage level based at least in part on the power mode; and using at least one of the first reference voltage level and the second reference voltage level for comparison against incoming data.

An exponentially-scaling switched impedance circuit includes: two or more impedance scaling circuits, wherein each impedance scaling circuit comprises: an input port; an output port; and a switched impedance circuit connected in parallel to the output port. Each impedance scaling circuit is configured to provide an effective impedance at the input port corresponding to a scaled-down version of the exponentially-scaling switched impedance circuit. The two or more impedance scaling circuits are connected in a cascade such that an input of an impedance scaling circuit is connected to an output of a previous impedance scaling circuit and/or an output of the impedance scaling circuit is connected to an input of a next impedance scaling circuit.

A method for generating a clock signal using a digital phase-locked loop includes updating a gain of a variable gain digital filter of the digital phase-locked loop using an estimate error of a current estimate of a phase and a frequency of an input clock signal and a measurement error of a measurement of the phase and the frequency of the input clock signal. The gain may include a proportional gain component and an integral gain component. The method may include calculating the current estimate of the phase and the frequency of the input clock signal based on a previous estimate of the phase and the frequency of the input clock signal, the measurement of the phase and the frequency of the input clock signal, and the gain of the variable gain digital filter. The gain may be updated every cycle of the input clock signal.

One inductive sensor is configured to maintain a fixed frequency in a resonant circuit. One apparatus includes an inductance-to-digital converter (LDC). The LDC includes a digital filter to measure an inductance change of a sensor and convert the inductance change to a digital value. The LDC further includes a digital control loop to maintain a fixed frequency in the sensor. The sensor forms an oscillator in the digital control loop. An output of the digital control loop is representative of the inductance change of the sensor.

Processing a digital bit stream and systems for implementing the methods are provided. The method includes dividing the digital bit stream into a plurality of data packets. In a first processing block performing a carrier recovery error calculation on a first portion of the plurality of data packets, comprising preforming a first phase locked loop (PLL) function on decimated data of the data packets and performing a carrier recovery operation on the first portion of the plurality of data packets. In a second processing block, in parallel with the processing of the first portion of the plurality of packets, performing the carrier recovery error calculation on a second portion of the plurality of data packets, comprising preforming the first PLL function on decimated data of the data packets and performing the carrier recovery operation on second portion of the plurality of data packets.

The disclosure provides a phase locked loop, PLL, for phase locking an output signal to a reference signal. The PLL comprises a reference path providing the reference signal to a first input of a phase detector, a feedback loop providing the output signal of the PLL as a feedback signal to a second input of the phase detector, a controllable oscillator generating the output signal based on at least a phase difference between reference and feedback signal, a digital-to-time converter, DTC, delaying a signal that is provided at one of the first and second input, a delay calculation path for calculating a DTC delay value. The PLL further comprises a randomization unit for generating and adding a random offset, i.e. a pseudo-random integer, to the delay value. The offset is such that a target output of the phase detector remains substantially unchanged.

To speed up output clock alignment in a digital phase locked loop wherein a controlled oscillator generates synthesizer pulses that are divided to produce output pulses at a predetermined normal spacing and time location, and wherein during an alignment procedure the output pulses are moved in time in response to a delay value obtained by comparing a phase of the output pulses with a phase applied to the controlled oscillator averaged over a number of synthesizer pulses in a feedback circuit to align said output pulses with a reference clock taking into account hardware delay, a group of the output pulses is advanced during the alignment procedure to reduce the spacing between them. After determining the delay value averaged over the group of output pulses subsequent output pulses are restored to their normal spacing and time locations.

A time-to-digital converter (TDC) circuit includes phase error calculation circuitry to: determine phase error values based on a time difference between a input reference clock and a feedback clock of a digital phase-locked loop (DPLL) circuit, the input reference clock and the feedback clock being unsynchronized; and provide the phase error values to a digital loop filter (DLF) of the DPLL circuit. The TDC circuit further includes clock generation circuitry to: generate a filter clock that asserts a clock pulse in response to detecting each last-received pulse of the input reference clock and the feedback clock; and provide the filter clock to the DLF concurrently with providing the phase error values to the DLF that are synchronized to the filter clock.

The present disclosure discloses an all-digital phase-locked loop. The all-digital phase-locked loop may include a time-to-digital conversion circuit configured to convert phase differences between a reference signal and a feedback signal into respective digital values and to output a first data signal and a second data signal corresponding to the respective digital values, a digital loop filter configured to select one of the first data signal and the second data signal as valid data and output a control signal by operating the valid data and a first register signal, a digitally controlled oscillator configured to generate an oscillation signal and control a frequency of the oscillation signal in response to the control signal, and a divider configured to divide the oscillation signal and output the feedback signal to the time-to-digital conversion circuit.

Performance indicator circuitry is provided for characterizing performance of a phase locked loop (PLL) in a phase path of a polar modulator or polar transmitter that is used to generate a phase modulated RF signal. The PLL includes an oscillator, a high pass path, and a low pass path. The low pass path includes a loop filter. The performance indicator circuitry includes first input circuitry and parameter calculation circuitry. The first input circuitry is configured to input a loop filter signal from the loop filter. The parameter calculation circuitry is configured to compute a value for a performance indicator based on the loop filter signal and control or characterize an aspect of operation of the PLL based on the value.