Methods and systems for a digitally controlled oscillator may comprise, for example, an all-digital all digital phase locked loop (ADPLL) for generating an output clock signal from a reference clock signal, the ADPLL comprising a thermometer pulse coder comprising a plurality of frequency control word signal lines. the thermometer pulse coder may be configured to generate a frequency control word from a binary encoded frequency control word, where the frequency control word may comprise hermometer coded signals and a pulse modulated dither signal, and may select a frequency control word signal line over which to transmit the pulse modulated dither signal and may transmit the thermometer coded signals over another of frequency control word signal lines. A digitally controlled oscillator may be configured to receive a frequency control word and generate an output clock signal at a frequency determined using at least the frequency control word.

A reconfigurable, digital phase-locked loop integrated circuit is disclosed which is coupleable to a reference frequency generator. A representative embodiment may include a memory storing a plurality of configuration parameters, at least one configuration parameter of specifying an output frequency; a reconfigurable frequency and delay generator configurable and reconfigurable in response to the configuration parameters to generate an output signal having the output frequency; and a digital controller adapted to access the memory and retrieve the plurality of configuration parameters, and to generate a plurality of control signals to the reconfigurable frequency and delay generator both to generate the output signal having the output frequency in response to the plurality of configuration parameters, and to match a phase of the output signal to an input signal phase.

A clock generator receives first and second clock signals, and input representing a desired frequency ratio. A comparison is made between frequencies of an output clock signal and the first clock signal, and a first error signal represents the difference between the desired frequency ratio and this comparison result. The first error signal is filtered. A comparison is made between frequencies of the output clock signal and the second clock signal, and a second error signal represents the difference between the filtered first error signal and this comparison result. The second error signal is filtered. A numerically controlled oscillator receives the filtered second error signal and generates an output clock signal. As a result, the output clock signal has the jitter characteristics of the first input clock signal over a useful range of jitter frequencies and the frequency accuracy of the second input clock signal.

In a phase locked loop composed of digital circuits, the circuit scale of a circuit that generates phase difference information is reduced. A multi-phase clock generation circuit generates a plurality of feedback clock signals having different phases. A feedback side frequency divider divides frequencies of the plurality of feedback clock signals and outputs the feedback clock signals as frequency-divided clock signals. A reference clock latch circuit holds the frequency-divided clock signals in synchronization with a reference clock signal and outputs a held value. A control circuit controls the frequencies of the plurality of feedback clock signals on the basis of the held value.

A receiver includes: an A/D converter that performs an analog digital conversion of an input signal; an equalizer that equalizes an output from the A/D converter, eliminates inter code interference and obtains a data output; a timing recovery part that generates a recovery clock from the data output of the equalizer; a detector that detects the timing when an input signal varies from a no-signal state and has reached a predetermined threshold; and an initial phase setting part that sets as the initial phase of the recovery clock by the timing recovery part, a timing when the predetermined time has elapsed after the timing detected by the detector.

An apparatus is provided which comprises: a frequency locked loop (FLL) comprising an oscillator including a plurality of delay stages, wherein an output of each delay stage is counted to determine a frequency of the FLL; and one or more circuitries coupled to the FLL to adjust a power supply to the FLL according to the determined frequency of the FLL.

Apparatus and methods for rotary traveling wave oscillators (RTWOs) are disclosed. In certain embodiments, an RTWO system include an RTWO ring that carries a traveling wave, a plurality of selectable capacitors distributed around the RTWO ring and each operable in a selected state and an unselected state, and a decoder system that controls selection of the plurality of selectable capacitors based on a frequency tuning code. The frequency tuning code includes a fine tuning code and a coarse tuning code, and the decoder system is operable to maintain a constant number of capacitors that toggle state for each value of the fine tuning code.

A phase and frequency detector receives a reference clock signal with a period error and receives a feedback clock signal from a feedback divider. The feedback divider circuit divides a clock signal from a voltage controlled oscillator. The feedback divider divides by different divide values during odd and even cycles of the reference clock signal to cause the feedback clock signal to have a period error that substantially matches the period error of the reference clock signal. The divider values supplied to the feedback divider are determined, at least in part, by the period error of the reference clock signal.

A circuit device includes a clock generation circuit, a signal generation circuit, a phase comparison circuit, and a processing circuit. The signal generation circuit generates a first signal making the transition at a transition timing of a first clock signal, a fine-judging signal making the transition at a transition timing of a second clock signal, a first coarse-judging signal making the transition at a transition timing of the second clock signal anterior to the fine-judging signal, and a second coarse-judging signal making the transition at a transition timing of the second clock signal posterior to the fine-judging signal. The phase comparison circuit performs the phase comparison between the second signal making the transition based on the first signal and each of the fine-judging signal, the first coarse-judging signal, and the second coarse-judging signal. The processing circuit sets the transition timing of the first signal and the transition timing of the fine-judging signal based on the phase comparison result, and converts a time difference between the first signal and the second signal into a digital value based on the setting result.

In a time-to-digital converter, a digital signal outputted by a phase information generator is inputted to each of the D terminals of first through Nth (N is a natural number equal to or greater than 2) D-type flip-flop circuits in a first flip-flop group, each of the D terminals is connected to one end of a first delay element, the C terminal of the first D-type flip-flop circuit is connected to another end of the first delay element, the other end of the first delay element is connected to an input terminal, and, when N, the number of flip-flop circuits in the first flip-flop group, is equal to or greater than 3, for each J a natural number from 2 to N−1, C terminal of the (J+1)th D-type flip-flop circuit is connected to one end of the Jth delay element and one end of the (J−1)th delay element is connected to the other end of the Jth delay element.