An audio in/out device includes an audible in/out transducer operable to convert an audible input signal to an audio receive (RX) signal and convert an audio transmit (TX) signal to an audible output signal. The audio in/out device further includes an audio receive/transmit (RX/TX) circuit operable to convert a digital TX signal to the audio TX signal for transmission to the audible in/out transducer, receive the audio RX signal from the audible in/out transducer, and convert the audio RX signal into a digital transmit/receive (Tx/Rx) signal. The digital Tx/Rx signal includes a representation of the audio RX signal.

A field device includes a detector and a converter communicative to the detector. The detector also may include, but is not limited to, a sensor, an analog-to-digital converter, and a first processor. The sensor may be configured to acquire an analog measurement signal. The analog-to-digital converter may be configured to convert the analog measurement signal to a digital signal. The first processor may be configured to convert the digital signal into a measurement value to generate a digital signal representing at least the measurement value. The converter may be configured to convert the digital signal representing at least the measurement value into an instrumentation signal to output the instrumentation signal. The detector may be configured to transmit the digital signal representing at least the measurement value and the analog measurement signal to the converter.

The present disclosure provides a signal conversion circuit and fingerprint identification system. The signal conversion circuit is configured to generate a first digital signal according to a first analog signal, and includes a comparator and counter. The comparator includes a first input terminal configured to receive the first analog signal, a second input terminal connected to a reference voltage generator and configured to receive a reference voltage, and an output terminal configured to output a second digital signal. The counter is connected to the output terminal, and is configured to generate a first digital signal. The signal conversion circuit according to the present disclosure has the advantages of simple circuit structure, small circuit area, low cost and low power consumption.

One example includes a pipelined analog-to-digital converter device. The pipelined analog-to-digital converter device includes a capacitive digital-to-analog converter, a first analog-to-digital converter, and a second analog-to-digital converter. The capacitive digital-to-analog converter includes a capacitor comprised of a top plate and a bottom plate, the capacitive digital-to-analog converter sampling an analog input signal applied to the pipelined analog-to-digital converter device while the capacitor is grounded, holding the sampled analog input while the top plate is floated, and outputting a residue voltage. The second analog-to-digital converter is coupled to the top plate of the capacitor, the second analog-to-digital converter producing a second digital representation of voltage on the top plate of the capacitor after the top plate is floated, wherein the second digital representation represents fine bits produced by the first stage of the pipelined analog-to-digital converter device.

An apparatus includes a processor, a Phase-Locked Loop Waveform Generator (PLLWG), a Voltage Controlled Oscillator (VCO), a demodulator, signal conditioning circuitry, and an Analog-to-Digital Converter (ADC). The processor generates control command signals, receives a digital data input signal, and performs spectrum analysis on the digital data input signal. The PLLWG is coupled to the processor, receives the control command signals, and generates a charge pump output signal based on the control command signals. The VCO is coupled to the PLLWG, receives a tuning signal based on the charge pump output signal, and outputs a VCO output signal based on the tuning signal. The demodulator receives an incoming modulated signal and the VCO output signal, and outputs an analog output signal based on the incoming modulated signal and the VCO output signal. The ADC converts the analog output signal into the digital data input signal.

A voltage or current regulator has a power DAC and ADC in a negative feedback loop, locked to a reference voltage or current. The ADC may have one or more parallel comparators followed by one or more parallel filters. The regulator may include a multiplexer to select between filter output signals and to forward the selected signal to the power DAC. The regulator may receive power management mode control codes to modify filter behavior and/or to select between multiple parallel filters. By modifying the loop behavior, the regulator is able to swiftly change between power management modes supporting different power level and noise profiles. Regulators with a single comparator can lock the output to a single reference voltage or current. Regulators with two comparators can regulate the output to vary within a range limited by an upper and a lower reference voltage or current.

Circuit and method for encoding an analog signal to a stream of bits at an Analog to Digital Converter (ADC) and subsequent reconstruction of the original signal from the bit stream at a Digital to Analog Converter (DAC), where the ADC module samples the analog signal at a sub-Nyquist rate and encodes the samples to a stream of bits. The bit steam is subsequently used to reconstruct the Nyquist-rate samples of the original analog signal at the DAC. The ADC samples the input signal in one of the two realizations of non-uniform sampling, namely, Random Sampling (RS) and Level Crossing (LC) sampling techniques, according to embodiments of the disclosed invention.

A converter may include multiple converter stages connected in series. Each converter stage may receive a clock signal and an analog input signal, and may generate an analog output signal and a digital output signal. Each converter stages may include an encoder generating the digital output signal, a decoder generating a reconstructed signal, a delaying converter generating a delayed signal, and an amplifier generating a residue signal, wherein the delayed signal may be a continuous current signal.

Digital focal plane arrays (DFPAs) with multiple counters per unit cell can be used to convert analog signals to digital data and to filter the digital data. Exemplary DFPAs include two-dimensional arrays of unit cells, where each unit cell is coupled to a corresponding photodetector in a photodetector array. Each unit cell converts photocurrent from its photodetector to a digital pulse train that is coupled to multiple counters in the unit cell. Each counter in each unit cell can be independently controlled to filter the pulse train by counting up or down and/or by transferring data as desired. For example, a unit cell may perform in-phase/quadrature filtering of homodyne- or heterodyne-detected photocurrent with two counters: a first counter toggled between increment and decrement modes with an in-phase signal and a second counter toggled between increment and decrement modes with a quadrature signal.

An integrated constant time delay circuit utilized in continuous-time (CT) analog-to-digital converters (ADCs) can be implemented with an RC lattice structure to provide, e.g., a passive all-pass lattice filter. Additional poles created by decoupling capacitors can be used to provide a low-pass filtering effect in some embodiments. A Resistor-Capacitor “RC” lattice structure can be an alternative to a constant-resistance Inductor-Capacitor “LC” lattice implementation. ADC architectures benefit from the RC implementation, due to its ease of impedance scaling and smaller area.