An integrated circuit includes an H-bridge circuit having a first output node for coupling to a high-side terminal of an inductor and a second output node for coupling to a low-side terminal of the inductor. A current source is coupled in series with a current sense FET between a digital upper supply voltage and the first output node, wherein during a fast decay mode, a gate of the current sense FET is coupled to be turned on. A current-sense comparator includes a first input coupled to a sensing node between the current source and the current sense FET, a second input coupled to the lower supply voltage and an output coupled to a driver control circuit.

A device includes a memory array and a sense amplifier (SA) coupled with the memory array and with an input/output (I/O) data line. The SA is to receive bits of data over the I/O data line in association with a program operation. A digital-to-analog converter (DAC) is coupled with the SA, the DAC to convert the bits of data to an analog voltage value. An analog memory element is coupled with the DAC, the analog memory element to store the analog voltage value for a period of time until the bits of data are programmed to the memory array.

An amplifier circuit comprises a first gain circuit path configured to provide a first signal gain to an input signal, a second gain circuit path configured to provide a second signal gain to an input signal, an auxiliary gain circuit path configured to provide an auxiliary signal gain to an auxiliary input signal, wherein the auxiliary signal gain is equal to the first signal gain minus the second signal gain, a summing circuit configured to sum the second gain signal path and the auxiliary signal path, and logic circuitry configured to change an output of the circuit between the first gain circuit path and the sum of the second gain signal path and the auxiliary signal path, and set the auxiliary input signal equal to the input signal before the changing.

Systems and methods are disclosed for full utilization of a data path's dynamic range. In certain embodiments, an apparatus may comprise a circuit including a first filter to digitally filter and output a first signal, a second filter to digitally filter and output a second signal, a summing node, and a first adaptation circuit. The summing node combine the first signal and the second signal to generate a combined signal at a summing node output. The first adaptation circuit may be configured to receive the combined signal, and filter the first signal and the second signal to set a dynamic amplitude range of the combined signal at the summing node output by modifying a first coefficient of the first filter and a second coefficient of the second filter based on the combined signal.

Disclosed is a sensor with compensation circuit for compensating offset by use of a switching circuit. The sensor has two operation modes for generating two output voltages, respectively. Offset is compensated by adding the two output voltages, and magnitude of the offset is calculated by subtracting the two output voltages. A noise threshold is set for checking if the circuit is affected by interference. When the circuit is affected by interference, the adding result of the two output voltages will be larger than the noise threshold, the output data will be hold and not updated, then a reminding signal will be issued to show that the circuit is affected by interference, and the output data flickers on a display unit when the adding result of the two output voltages is larger than the noise threshold for showing the circuit is affected by interference.

A dither capacitor, separate from the capacitor sampling the input signal, can be used to inject the additive dither in the switched-capacitor network of the track and hold circuit. This implementation can be referred to as a split-capacitor dither injection. The dither capacitor can be connected to a summing node of the switched-capacitor network. Using a separate capacitor allows the dither to be isolated from the capacitor that is sampling the input signal and avoids kick-back errors.

A flyback converter is provided that detects a load-transient-produced increase in the output current to more quickly detect and respond to the load transient.

Provided are a data transmission method, a circuit board, a data transmission apparatus, a storage medium and an electronic apparatus. The data transmission method is applied between a chip and an analog-to-digital/ digital-to-analog (AD/DA) converter and includes transmitting first data through a first transmission channel. The first transmission channel includes invalid bits in a second transmission channel, the second transmission channel is configured to transmit second data, the first data includes customized data, and the second data includes traffic data.

An impedance measuring apparatus is disclosed. The impedance measuring apparatus includes an input current generator configured to generate a sinusoidal input signal of a carrier frequency, a first electrode configured to apply the sinusoidal input signal to an object which has an impedance, a second electrode configured to receive an amplitude modulated signal from the object, a first amplifier configured to amplify the received amplitude modulated signal and output a first amplified signal, a baseline signal subtractor configured to subtract a baseline signal generated based on the first amplified signal from the amplitude modulated signal and output a subtraction modulated signal, an analog-to-digital converter (ADC) configured to convert the subtraction modulated signal to a digital modulated signal, and an impedance measurer configured to measure the impedance based on the digital modulated signal.

An image sensor may contain an array of imaging pixels. Each pixel column outputs signals that are read out using a successive approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC may include at least first and second input sampling capacitors, a comparator, a capacitive digital-to-analog converter (CDAC), and associated control circuitry. If desired, the SAR ADC may include a bank of more than two input sampling capacitors alternating between sampling and conversion. The first capacitor may be used to sample an input signal while conversion for the second capacitor is taking place. Prior to conversion, an input voltage of the comparator and an output voltage of the CDAC may be initialized. During conversion of the signal on the first capacitor, the first capacitor is embedded within the SAR ADC feedback loop to prevent charge sharing between the input sampling capacitor and the CDAC, thereby mitigating potential capacitor mismatch issues.