A high resolution analog to digital converter (ADC) with improved bandwidth senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. In addition, quantization noise is subtracted from the digital output signal thereby extending the operational bandwidth of the ADC. In certain examples, the operational bandwidth of the ADC extends up to 100 s of kHz (e.g., 200-300 kHz), or even higher.

A multi-stage analog-to-digital converter (ADC) suitable for low power applications, such as glucose monitoring, may be required to digitize a slow-moving signal. As such, a multi-stage ADC must be versatile. Accordingly, the multi-stage ADC can be configured to operate at different bandwidths and resolutions through the use of ADC stages that can be enabled or disabled in an exchange between resolution and speed. Each ADC stage digitizes an input signal (e.g., a voltage or a current) using an analog comparison to access a lookup table for a digital signal that represents the input signal at a particular accuracy. Unlike other multi-stage approaches, the digitization is asynchronous (i.e., requires no clock) and can provide simplicity, speed, and low-power operation to the multi-stage ADC.

A multi-stage analog-to-digital converter (ADC) suitable for low power applications, such as glucose monitoring, may be required to digitize a slow-moving signal. As such, a multi-stage ADC must be versatile. Accordingly, the multi-stage ADC can be configured to operate at different bandwidths and resolutions through the use of ADC stages that can be enabled or disabled in an exchange between resolution and speed. Each ADC stage digitizes an input signal (e.g., a voltage or a current) using an analog comparison to access a lookup table for a digital signal that represents the input signal at a particular accuracy. Unlike other multi-stage approaches, the digitization is asynchronous (i.e., requires no clock) and can provide simplicity, speed, and low-power operation to the multi-stage ADC.

A digital converter and a controlling method are disclosed. The digital converter includes a sensing oscillator including a plurality of tri-state buffers configured to generate a sensing clock period signal corresponding to a change value of at least one of a resistive sensor and a capacitive sensor, a reference oscillator configured to generate a predetermined fixed clock period signal, a processor configured to change a connection state of the plurality of tri-state buffers, a frequency divider configured to scale up the generated sensing clock period signal based on a predetermined value; and a counter configured to count the scaled up sensing clock period signal based on the generated fixed clock cycle signal and output a counted digital value.

A decision-feedback equalizer (DFE) samples an analog input signal against M references during the same symbol time to produce M speculative samples. Select logic in the DFE, then decodes N bits resolved previously for previous symbol times to select one of the M speculative samples as the present resolved bit. The present resolved bit is then stored as the most recent previously resolved bit in preparation for the next symbol time. The select logic can be can be programmable to accommodate process, environmental, and systematic variations.

A method in a transmitter circuit of generating a signal comprising a first sequence of OFDM symbols, which are to be transmitted within a frequency sub band of a second sequence of OFDM symbols is disclosed. A first cyclic prefix (CP) of the second sequence of OFDM symbols has a first duration, and a second CP of the second sequence of OFDM symbols has a second duration. In order to generate both the first and the second cyclic prefix with an integer number of equidistant samples, a first sampling rate is required. The method comprises generating the signal comprising the first sequence of OFDM symbols at a second sampling rate, lower than the first sampling rate, and adjusting a sampling phase during CPs.

A multi-stage analog-to-digital converter (ADC) suitable for low power applications, such as glucose monitoring, may be required to digitize a slow-moving signal. As such, a multi-stage ADC must be versatile. Accordingly, the multi-stage ADC can be configured to operate at different bandwidths and resolutions through the use of ADC stages that can be enabled or disabled in an exchange between resolution and speed. Each ADC stage digitizes an input signal (e.g., a voltage or a current) using an analog comparison to access a lookup table for a digital signal that represents the input signal at a particular accuracy. Unlike other multi-stage approaches, the digitization is asynchronous (i.e., requires no clock) and can provide simplicity, speed, and low-power operation to the multi-stage ADC.

A method in a transmitter circuit of generating a signal comprising a first sequence of OFDM symbols, which are to be transmitted within a frequency sub band of a second sequence of OFDM symbols is disclosed. A first cyclic prefix (CP) of the second sequence of OFDM symbols has a first duration, and a second CP of the second sequence of OFDM symbols has a second duration. In order to generate both the first and the second cyclic prefix with an integer number of equidistant samples, a first sampling rate is required. The method comprises generating the signal comprising the first sequence of OFDM symbols at a second sampling rate, lower than the first sampling rate, and adjusting a sampling phase during CPs.

A radio frequency transmitter including two digital to analog converter circuits. The two radio frequency digital to analog converter circuits are configured to operate independently or operating in unison. Operating independently includes each radio frequency digital to analog converter circuit of the two radio frequency digital to analog converter circuits receiving separate baseband signals and separate local oscillation inputs. Operating in unison includes both of the two radio frequency digital to analog converter circuits receiving a single baseband signal and a single local oscillation input. The two radio frequency digital to analog converter circuits are configured to change between operating independently and operating in unison.

A leakage compensation circuit includes a compensation digital to analog converter (DAC) and an adjustment circuit. The compensation DAC is configured to: receive a first digital signal associated with a transmitter of a transceiver; generate a compensation analog signal using the first digital signal; and provide the compensation analog signal to a receiver of the transceiver. The adjustment circuit is configured to generate the first digital signal by adjusting a second digital signal from the transmitter based on one or more adjustment parameters.