According to one aspect, a semiconductor device (1) includes: an input circuit (11_1) configured to receive an analog signal, the analog signal and a digital signal being selectively input; an input circuit (11_4) configured to be driven by a power supply common to the input circuit (11_1) and receive a digital signal, the digital signal and an analog signal being selectively input; an AD converter (15) configured to perform AD conversion of the analog signal input to the input circuit (11_1); an edge detection circuit (12) configured to detect an edge of the digital signal input to the input circuit (11_4); and a control unit (13) configured to execute predetermined processing on a result of the AD conversion by the AD converter (15) based on a result of the detection by the edge detection circuit (12).

A method in a transmitter circuit (200) of generating a signal comprising a first sequence of OFDM symbols, which are to be transmitted within a frequency sub band of a second sequence of OFDM symbols is disclosed. A first CP of the second sequence of OFDM symbols has a first duration, and a second CP of the second sequence of OFDM symbols has a second duration. In order to generate both the first and the second cyclic prefix with an integer number of equidistant samples, a first sampling rate is required. The method comprises generating (100) the signal comprising the first sequence of OFDM symbols at a second sampling rate, lower than the first sampling rate, and adjusting (110) a sampling phase during CPs.

According to one aspect, a semiconductor device (1) includes: an input circuit (11_1) configured to receive an analog signal, the analog signal and a digital signal being selectively input; an input circuit (11_4) configured to be driven by a power supply common to the input circuit (11_1) and receive a digital signal, the digital signal and an analog signal being selectively input; an AD converter (15) configured to perform AD conversion of the analog signal input to the input circuit (11_1); an edge detection circuit (12) configured to detect an edge of the digital signal input to the input circuit (11_4); and a control unit (13) configured to execute predetermined processing on a result of the AD conversion by the AD converter (15) based on a result of the detection by the edge detection circuit (12).

A sigma-delta modulator arrangement includes a continuous-time sigma-delta modulator with at least one modulator stage, a digital integrator and a given number of switches. The switches are arranged and configured to convert the continuous-time sigma-delta modulator into a first order incremental sigma-delta analog-to-digital converter comprising the digital integrator. At least a first modulator stage of the continuous-time sigma-delta-modulator, which is coupled with an input of the continuous-time sigma-delta modulator, includes at least one tuning element for adjusting an input signal and/or a feedback signal which are supplied to the first modulator stage.

A decision-feedback equalizer (DFE) samples an analog input signal against M references during the same symbol time to produce M speculative samples. Select logic in the DFE then decodes N bits resolved previously for previous symbol times to select one of the M speculative samples as the present resolved bit. The present resolved bit is then stored as the most recent previously resolved bit in preparation for the next symbol time. The select logic can be can be programmable to accommodate process, environmental, and systematic variations.

A device, system, and method of a programmable circuit configured to operate in a buffered drive mode and blanking mode is disclosed. The programmable circuit includes a continuous-time digital-to-analog converter (CTDAC), a continuous-time block (CTB), coupled to the CTDAC, and a sample and hold (SH) circuit coupled to the CTDAC and the CTB. The programmable circuit is configured to operate in a buffered drive mode to buffer an output signal from the CTDAC. The programmable circuit, in buffered drive mode, is further configured to operate in a blanking mode to cause the SH circuit to perform a blanking operation on the CTDAC output signal.

A decision-feedback equalizer (DFE) samples an analog input signal against M references during the same symbol time to produce M speculative samples. Select logic in the DFE then decodes N bits resolved previously for previous symbol times to select one of the M speculative samples as the present resolved bit. The present resolved bit is then stored as the most recent previously resolved bit in preparation for the next symbol time. The select logic can be can be programmable to accommodate process, environmental, and systematic variations.

The present disclosure relates to an integrated circuit with at least a first channel and a second channel. Each channel includes at least a DAC. The integrated circuit also includes a number of circuit elements interconnected between the channels. The circuit elements can be changed between a short circuit state and an open circuit state. Normally, each channel will operate independently of one another, using only the circuit components in its respective channel. However, the circuit elements are arranged to allow a user to combine part of the second channel with the first channel to improve the functionality and performance of the first channel. In particular, a state of the circuit elements can be chosen to combine components of the second channel with the first channel. For example, components (e.g. a sub-stage) of the second channel can be connected in parallel with corresponding components (e.g. a corresponding sub-stage) of the first channel. This may reduce the number of available channels, since the second channel can no longer be used as an independent channel. However, the performance of the first channel is enhanced. The presence of the circuit elements allow an end user to decide whether to sacrifice channel count for performance enhancements. For example, the user can provide user input to the integrated circuit to select how the channels are interconnected. Moreover, the integrated circuit does not use additional redundant circuitry to improve the first channel, and rather takes components from the second channel. As such, the integrated circuit can have a reduced size.

A configurable output stage for a DAC channel can include an output stage that can receive an analog output from a DAC and outputs a signal to an output terminal. The output stage can be configurable between a voltage mode and a current mode. In the voltage mode, the output stage can supply the analog signal to the output terminal as a voltage signal. In the current mode, the output stage can supply the analog signal to the output signal as a current signal. The output stage can receive user input to select the desired mode. Consequently, an integrated circuit can be implemented with multiple DAC channels, each having the configurable output stage. A user can choose how many channels they want to operate in a voltage output mode, and how many channels they want to operate in a current output mode, depending on their individual requirements.