A multiplexing device for a digital-to-analog conversion circuit and an analog-to-digital conversion circuit in a storage and calculation integrated chip, comprising a digital-to-analog conversion circuit (DAC) module, an analog vector-matrix multiplication operation circuit(AMAC) module, an analog-to-digital conversion circuit(ADC) module, a first many-to-one multiplexer (M1-MUX) module, a second M1-MUX module, a first one-to-many multiplexer (1M-MUX) module, a second 1M-MUX module, and a switching transistor module. At an AMAC input end, each DAC corresponds to a plurality of input ends and is shared with the first 1M-MUX module in a time multiplexing mode by means of the first M1-MUX module; at an AMAC output end, each ADC corresponds to a plurality of output ends, and is shared with the second 1M-MUX module in a time multiplexing mode by means of the second M1-MUX module; the number of DACs and ADCs is reduced, and the chip area is reduced.

In some embodiments, an analog-to-digital converter (ADC) comprises a loop filter configured to produce an error signal based on a difference between an analog input signal and a feedback signal. The ADC also comprises a main comparator set comprising one or more main comparators, the main comparator set configured to digitize the error signal and further configured to drive a main digital-to-analog converter (DAC). The ADC further comprises an auxiliary comparator set comprising a plurality of auxiliary comparators, the auxiliary comparator set configured to digitize the error signal when the ADC is in a runaway state and further configured to drive an auxiliary DAC to bring the error signal into a predetermined range.

In some embodiments, an analog-to-digital converter (ADC) comprises a loop filter configured to produce an error signal based on a difference between an analog input signal and a feedback signal. The ADC also comprises a main comparator set comprising one or more main comparators, the main comparator set configured to digitize the error signal and further configured to drive a main digital-to-analog converter (DAC). The ADC further comprises an auxiliary comparator set comprising a plurality of auxiliary comparators, the auxiliary comparator set configured to digitize the error signal when the ADC is in a runaway state and further configured to drive an auxiliary DAC to bring the error signal into a predetermined range.

In some embodiments, an analog-to-digital converter (ADC) comprises a loop filter configured to produce an error signal based on a difference between an analog input signal and a feedback signal. The ADC also comprises a main comparator set comprising one or more main comparators, the main comparator set configured to digitize the error signal and further configured to drive a main digital-to-analog converter (DAC). The ADC further comprises an auxiliary comparator set comprising a plurality of auxiliary comparators, the auxiliary comparator set configured to digitize the error signal when the ADC is in a runaway state and further configured to drive an auxiliary DAC to bring the error signal into a predetermined range.

In some embodiments, an analog-to-digital converter (ADC) comprises a loop filter configured to produce an error signal based on a difference between an analog input signal and a feedback signal. The ADC also comprises a main comparator set comprising one or more main comparators, the main comparator set configured to digitize the error signal and further configured to drive a main digital-to-analog converter (DAC). The ADC further comprises an auxiliary comparator set comprising a plurality of auxiliary comparators, the auxiliary comparator set configured to digitize the error signal when the ADC is in a runaway state and further configured to drive an auxiliary DAC to bring the error signal into a predetermined range.

An improved system and method for reducing the ambient noise experienced by a user listening to an earpiece without the use of a microphone is disclosed. An ambient noise signal created by the sound pressure wave of the ambient noise acting on the earpiece transducer is obtained. In some embodiments, the ambient noise signal is inverted and fed back, and the inverted signal is added to the intended audio signal being sent to the earpiece so that the ambient noise is cancelled. In other embodiments, a processor receives the ambient noise signal and predicts the modification to the intended audio signal needed to counteract the ambient noise. The ambient noise signal may be obtained by comparing the actual signal across the earpiece transducer to the intended audio signal, or by detecting variations in the current across the transducer from the current generated to drive the transducer.

An improved system and method for reducing the ambient noise experienced by a user listening to an earpiece without the use of a microphone is disclosed. An ambient noise signal created by the sound pressure wave of the ambient noise acting on the earpiece transducer is obtained. In some embodiments, the ambient noise signal is inverted and fed back, and the inverted signal is added to the intended audio signal being sent to the earpiece so that the ambient noise is cancelled. In other embodiments, a processor receives the ambient noise signal and predicts the modification to the intended audio signal needed to counteract the ambient noise. The ambient noise signal may be obtained by comparing the actual signal across the earpiece transducer to the intended audio signal, or by detecting variations in the current across the transducer from the current generated to drive the transducer.

A mobile phone and/or mobile device carrying case comprising openings on one side or corner placed adjacently on case allowing fasteners into the openings. To effect transport and fashion, mounts are fastened into or onto the fasteners. The mounts, positioned adjacently, allow the straps to connect to each mount enabling the mobile phone and/or mobile device carrying case to be held hands free around the shoulder, neck, and chest area.

A transceiver including: a reconfigurable circuit including a plurality of units including at least a converter, the converter including: a digital-to-analog converter (DAC); successive approximation register (SAR) logic configured to selectively couple to the DAC; and a plurality of switches configured to reconfigure the plurality of units of the reconfigurable circuit to operate the transceiver in a receive mode or transmit mode.

A transceiver including: a reconfigurable circuit including a plurality of units including at least a converter, the converter including: a digital-to-analog converter (DAC); successive approximation register (SAR) logic configured to selectively couple to the DAC; and a plurality of switches configured to reconfigure the plurality of units of the reconfigurable circuit to operate the transceiver in a receive mode or transmit mode.