A driver arrangement (10) comprises a digital controller (11) that is configured to receive a digital input signal (SDI) and a driver (12) that comprises a driver input (14) and a driver output (15) and is configured to provide an analog output signal (SANO) at the driver output (15). The driver arrangement (10) comprises a coupling circuit (13) that comprises a digital-to-analog converter (19) and a feedback circuit (24). The digital-to-analog converter (19) comprises a converter input (20) coupled to the digital controller (11) and a converter output (21) coupled to the driver input (14). The feedback circuit (24) is coupled to the driver output (15) and to a feedback input (17) of the digital controller (11).

A driver arrangement (10) comprises a digital controller (11) that is configured to receive a digital input signal (SDI) and a driver (12) that comprises a driver input (14) and a driver output (15) and is configured to provide an analog output signal (SANO) at the driver output (15). The driver arrangement (10) comprises a coupling circuit (13) that comprises a digital-to-analog converter (19) and a feedback circuit (24). The digital-to-analog converter (19) comprises a converter input (20) coupled to the digital controller (11) and a converter output (21) coupled to the driver input (14). The feedback circuit (24) is coupled to the driver output (15) and to a feedback input (17) of the digital controller (11).

In some embodiments, an analog-to-digital converter (ADC) comprises a loop filter configured to produce an error signal based on a difference between an analog input signal and a feedback signal. The ADC also comprises a main comparator set comprising one or more main comparators, the main comparator set configured to digitize the error signal and further configured to drive a main digital-to-analog converter (DAC). The ADC further comprises an auxiliary comparator set comprising a plurality of auxiliary comparators, the auxiliary comparator set configured to digitize the error signal when the ADC is in a runaway state and further configured to drive an auxiliary DAC to bring the error signal into a predetermined range.

In some embodiments, an analog-to-digital converter (ADC) comprises a loop filter configured to produce an error signal based on a difference between an analog input signal and a feedback signal. The ADC also comprises a main comparator set comprising one or more main comparators, the main comparator set configured to digitize the error signal and further configured to drive a main digital-to-analog converter (DAC). The ADC further comprises an auxiliary comparator set comprising a plurality of auxiliary comparators, the auxiliary comparator set configured to digitize the error signal when the ADC is in a runaway state and further configured to drive an auxiliary DAC to bring the error signal into a predetermined range.

Provided is programmable circuit for interfacing with a field device. The circuit includes only one analog-to-digital converter (ADC) configured to receive from the field device one from the group including a current signal and a voltage signal. The received one signal has frequency shift keying tones (FSK) superimposed thereon, the ADC being configured to extract information from the received one signal and the FSK tones simultaneously. Also included is only one digital-to-analog converter configured to drive an output signal to the field device, the output signal (i) including one from the group including a current signal and a voltage signal and (ii) being summed with an FSK-modulated signal.

A sensor for ultrasonically measuring a portion of a structure, the sensor comprising: a transducer for converting an analog transmit signal to an ultrasonic transmit signal, and for converting an ultrasonic reflected signal to an analog reflected signal; a housing integrated with the transducer and containing at least: a processor; a wireless data transmitter for transmitting wirelessly a data signal from the processor; a transmit and receive circuit for transmitting an analog transmit signal to the transducer in response to a transmit trigger from the processor, and for receiving an analog reflected signal from the transducer; an A/D converter for digitizing only a portion of the analog reflected signal in response to a sample trigger from the processor; a battery to supply power to the processor, the wireless data transmitter, the transmit and receive circuit, and the A/D converter; memory operatively connected to the processor and configured to instruct the processor to execute the following steps: repeatedly triggering the transmit and receive circuit and the A/D converter to obtain a digitized composite signal through time-equivalent sampling; processing the digitized composite reflected signal to generate an A-scan signal; and wirelessly transmitting the data signal based on the A-scan signal for transmission to a discrete collection device.

A sensor for ultrasonically measuring a portion of a structure, the sensor comprising: a transducer for converting an analog transmit signal to an ultrasonic transmit signal, and for converting an ultrasonic reflected signal to an analog reflected signal; a housing integrated with the transducer and containing at least: a processor; a wireless data transmitter for transmitting wirelessly a data signal from the processor; a transmit and receive circuit for transmitting an analog transmit signal to the transducer in response to a transmit trigger from the processor, and for receiving an analog reflected signal from the transducer; an A/D converter for digitizing only a portion of the analog reflected signal in response to a sample trigger from the processor; a battery to supply power to the processor, the wireless data transmitter, the transmit and receive circuit, and the A/D converter; memory operatively connected to the processor and configured to instruct the processor to execute the following steps: repeatedly triggering the transmit and receive circuit and the A/D converter to obtain a digitized composite signal through time-equivalent sampling; processing the digitized composite reflected signal to generate an A-scan signal; and wirelessly transmitting the data signal based on the A-scan signal for transmission to a discrete collection device.

The present disclosure provides an analog readout preprocessing circuit for a CMOS image sensor and a control method thereof. The analog readout preprocessing circuit comprises an extended count-type integration cycle-successive approximation hybrid analog-to-digital conversion capacitor network 1 configured to achieve readout and analog-to-digital conversion of signals output from the CMOS image sensor; an operational amplifier configured to utilize virtual short of two input terminals of the operational amplifier and the charge conservation principle, to achieve a function of extended count-type integration cycle-successive approximation hybrid analog-to-digital conversion, where the extended count-type integration can effectively reduce a thermal noise and a flicker noise within the image sensor; a comparator configured to compare voltages at two terminals to achieve a function of quantization of signals; and a control signal generator configured to provide control signals.

The present disclosure provides an analog readout preprocessing circuit for a CMOS image sensor and a control method thereof. The analog readout preprocessing circuit comprises an extended count-type integration cycle-successive approximation hybrid analog-to-digital conversion capacitor network 1 configured to achieve readout and analog-to-digital conversion of signals output from the CMOS image sensor; an operational amplifier configured to utilize virtual short of two input terminals of the operational amplifier and the charge conservation principle, to achieve a function of extended count-type integration cycle-successive approximation hybrid analog-to-digital conversion, where the extended count-type integration can effectively reduce a thermal noise and a flicker noise within the image sensor; a comparator configured to compare voltages at two terminals to achieve a function of quantization of signals; and a control signal generator configured to provide control signals.

A transceiver including: a reconfigurable circuit including a plurality of units including at least a converter, the converter including: a digital-to-analog converter (DAC); successive approximation register (SAR) logic configured to selectively couple to the DAC; and a plurality of switches configured to reconfigure the plurality of units of the reconfigurable circuit to operate the transceiver in a receive mode or transmit mode.