Technologies directed to cable-loss compensation are described. An apparatus includes a triplexer, a front-end module (FEM) circuit, and a control circuit. The triplexer is coupled to a radio frequency (RF) cable. The triplexer receives a first RF signal and a DC power signal from a device via the RF cable and sends a detection signal being indicative of a transmit power level of the first RF signal to the device via the RF cable. The transmit power level includes an insertion loss of the RF cable. The FEM circuit is coupled to the triplexer and includes a power amplifier (PA). The control circuit is coupled to the triplexer and measures the transmit power level of the first RF signal and converts the first RF signal into the detection signal. The control circuit sends the detection signal back to the device via the RF cable and enables the PA.

Technologies directed to cable-loss compensation are described. An apparatus includes a triplexer, a front-end module (FEM) circuit, and a control circuit. The triplexer is coupled to a radio frequency (RF) cable. The triplexer receives a first RF signal and a DC power signal from a device via the RF cable and sends a detection signal being indicative of a transmit power level of the first RF signal to the device via the RF cable. The transmit power level includes an insertion loss of the RF cable. The FEM circuit is coupled to the triplexer and includes a power amplifier (PA). The control circuit is coupled to the triplexer and measures the transmit power level of the first RF signal and converts the first RF signal into the detection signal. The control circuit sends the detection signal back to the device via the RF cable and enables the PA.

A method for measuring a complex impedance of a plurality of battery cells in a battery pack comprises controlling an excitation current through the plurality of battery cells in the battery pack; receiving, in a single common measurement circuit, a plurality of voltage signals corresponding to the plurality of battery cells; measuring the excitation current; and calculating a complex impedance of each of the battery cells in the plurality of battery cells based on the plurality of voltage signals and the measured excitation current in a single measurement cycle using either one analog-to-digital converter (ADC) per battery cell or two matched ADCs per battery cell.

A method for measuring a complex impedance of a plurality of battery cells in a battery pack comprises controlling an excitation current through the plurality of battery cells in the battery pack; receiving, in a single common measurement circuit, a plurality of voltage signals corresponding to the plurality of battery cells; measuring the excitation current; and calculating a complex impedance of each of the battery cells in the plurality of battery cells based on the plurality of voltage signals and the measured excitation current in a single measurement cycle using either one analog-to-digital converter (ADC) per battery cell or two matched ADCs per battery cell.

Systems, devices, and methods related to low-noise, high-accuracy single-ended continuous-time sigma-delta (CTSD) analog-to-digital converter (ADC) are provided. An example single-ended CTSD ADC includes a pair of input nodes to receive a single-ended input signal and input circuitry. The input circuitry includes a pair of switches, each coupled to one of the pair of input nodes; and an amplifier to provide a common mode signal at a pair of first nodes, each before one of the pair of switches. The single-ended CTSD ADC further includes digital-to-analog converter (DAC) circuitry; and integrator circuitry coupled to the input circuitry and the DAC circuitry via a pair of second nodes.

Disclosed herein are devices, systems, and methods for improved demodulation. In one embodiment, a demodulator includes an input port configured to receive an analog input signal having a first frequency spectrum, a delta-sigma modulator electrically coupled with the input port, a digital downconverter electrically coupled with the delta-sigma modulator, and a filter electrically coupled with the digital downconverter. The filter is configured for a passband having a second frequency spectrum. The demodulator also includes an output port electrically coupled with the filter. The output port is configured to provide an output signal having the second frequency spectrum.

Disclosed herein are devices, systems, and methods for improved demodulation. In one embodiment, a demodulator includes an input port configured to receive an analog input signal having a first frequency spectrum, a delta-sigma modulator electrically coupled with the input port, a digital downconverter electrically coupled with the delta-sigma modulator, and a filter electrically coupled with the digital downconverter. The filter is configured for a passband having a second frequency spectrum. The demodulator also includes an output port electrically coupled with the filter. The output port is configured to provide an output signal having the second frequency spectrum.

Certain aspects of the present disclosure provide techniques for processing machine learning model data with a machine learning task accelerator, including: configuring one or more signal processing units (SPUs) of the machine learning task accelerator to process a machine learning model; providing model input data to the one or more configured SPUs; processing the model input data with the machine learning model using the one or more configured SPUs; and receiving output data from the one or more configured SPUs.

Certain aspects of the present disclosure provide techniques for processing machine learning model data with a machine learning task accelerator, including: configuring one or more signal processing units (SPUs) of the machine learning task accelerator to process a machine learning model; providing model input data to the one or more configured SPUs; processing the model input data with the machine learning model using the one or more configured SPUs; and receiving output data from the one or more configured SPUs.

An apparatus for analog-to-digital conversion is provided. The apparatus includes a first analog-to-digital converter (ADC) configured to receive an input signal and convert the input signal to a sequence of M-bit digital values. The apparatus further includes a second ADC including a plurality of time-interleaved sub-ADCs each being configured to receive the input signal and at least one M-bit digital value of the sequence of M-bit digital values. Further, each of the plurality of time-interleaved sub-ADCs is configured to convert the input signal to a respective sequence of B-bit digital values using the at least one M-bit digital value of the sequence of M-bit digital values. M and B are integers with M<B.