A semiconductor memory apparatus may include: a data adjusting circuit configured to conditionally adjust a weight data value for a MAC (Multiplication and ACcumulation) operation based on comparing the weight data value to a reference data value, and generate flag information indicating whether the weight data value has been adjusted; a memory cell array circuit configured to store the adjusted weight data value outputted from the data adjusting circuit; and a data calculation circuit configured to recover, on the flag information, a result based on the weight data value from a result based on the adjusted weight data value to perform the MAC operation on an input data value and the weight data value.

A ratiometric analog-to-digital conversion circuit includes a first voltage range operation circuit configured to use a first power supply voltage of a first voltage range, and output an analog signal corresponding to an external input signal; and a second voltage range operation circuit configured to use a second power supply voltage of a second voltage range, generate a digital value by analog-to-digital converting the analog signal, feed back the digital value for analog-to-digital conversion, and output a digital signal corresponding to the digital value and proportional to the input signal.

Herein disclosed is an example analog-to-digital converter (ADC) and methods that may be performed by the ADC. The ADC may derive a first code that approximates a combination of an analog input value of the ADC and a dither value for the ADC sampled on a capacitor array. The ADC may further derive a second code to represent a residue of the combination with respect to the first code applied to the capacitor array. The ADC may combine the numerical value of the first code and the numerical value of the second code to produce a combined code applied to the capacitor array for deriving a digital output code. Combining the numerical value of the first code and the numerical value of the second code in the digital domain can provide for greater analog-to-digital (A/D) conversion linearity.

A transmission circuit includes a power amplifier, a power amplifier forestage circuit and a signal strength adjusting circuit. The power amplifier is configured to amplify an input signal to output an output signal. The power amplifier forestage circuit is configured to output the input signal. The signal strength adjusting circuit includes a conversion circuit, a processing circuit and a storage unit. The conversion circuit is configured to convert the voltage of the output signal into an operation value. The processing circuit is configured to perform an operation according to a target index value stored by the storage unit and the operation value to obtain a differential value. The processing circuit is further configured to adjust the input signal outputted by the power amplifier forestage circuit according to the differential value, so that the power of the output signal is maintained at a target power value.

A transmission circuit includes a power amplifier, a power amplifier forestage circuit and a signal strength adjusting circuit. The power amplifier is configured to amplify an input signal to output an output signal. The power amplifier forestage circuit is configured to output the input signal. The signal strength adjusting circuit includes a conversion circuit, a processing circuit and a storage unit. The conversion circuit is configured to convert the voltage of the output signal into an operation value. The processing circuit is configured to perform an operation according to a target index value stored by the storage unit and the operation value to obtain a differential value. The processing circuit is further configured to adjust the input signal outputted by the power amplifier forestage circuit according to the differential value, so that the power of the output signal is maintained at a target power value.

A delta-sigma modulator may include a loop filter, a quantizer, an input gain element having a programmable input gain and coupled between an input of the delta-sigma modulator and an input of the loop filter, a feedforward gain element having a programmable feedforward gain and coupled between the input of the delta-sigma modulator and an output of the loop filter, and a quantizer gain element having a quantizer gain and coupled between the output of the loop filter and an input of the quantizer. The programmable input gain is controlled in order to control a variable gain of the delta-sigma modulator. The programmable feedforward gain is controlled to be equal to the ratio of the programmable input gain and the quantizer gain such that the delta-sigma modulator has a fixed phase response.

Systems and methods for data collection for an industrial heating process are disclosed. The system according to one embodiment can include a plurality of data collectors, including a swarm of self-organized data collector members, wherein the swarm of self-organized data collector members organize to enhance data collection based on at least one of capabilities and conditions of the data collector members of the swarm, and wherein the plurality of data collectors is coupled to a plurality of input channels for acquiring collected data relating to the industrial heating process, and a data acquisition and analysis circuit for receiving the collected data via the plurality of input channels and structured to analyze the received collected data using a neural network to monitor a plurality of conditions relating to the industrial heating process.

Systems and methods for data collection for an industrial heating process are disclosed. The system according to one embodiment can include a plurality of data collectors, including a swarm of self-organized data collector members, wherein the swarm of self-organized data collector members organize to enhance data collection based on at least one of capabilities and conditions of the data collector members of the swarm, and wherein the plurality of data collectors is coupled to a plurality of input channels for acquiring collected data relating to the industrial heating process, and a data acquisition and analysis circuit for receiving the collected data via the plurality of input channels and structured to analyze the received collected data using a neural network to monitor a plurality of conditions relating to the industrial heating process.

Examples herein relate to circuits for computing vector-matrix multiplications involving negative values. A first memory crossbar array may be mapped to a first matrix which includes the positive values of an input matrix. A second memory crossbar array may be mapped to a second matrix which includes the negative values of the input matrix. An analog-to-digital converter may generate digital intermediate multiplication results based on analog results computed by the memory crossbar arrays. The digital intermediate multiplication results may include an intermediate result corresponding to a multiplication of each of the first vector and second vector with each of the first matrix and the second matrix. A controller may aggregate the digital intermediate results to generate a combined multiple result that represents the vector-matrix multiplication of the input vector and the input matrix.

Examples herein relate to circuits for computing vector-matrix multiplications involving negative values. A first memory crossbar array may be mapped to a first matrix which includes the positive values of an input matrix. A second memory crossbar array may be mapped to a second matrix which includes the negative values of the input matrix. An analog-to-digital converter may generate digital intermediate multiplication results based on analog results computed by the memory crossbar arrays. The digital intermediate multiplication results may include an intermediate result corresponding to a multiplication of each of the first vector and second vector with each of the first matrix and the second matrix. A controller may aggregate the digital intermediate results to generate a combined multiple result that represents the vector-matrix multiplication of the input vector and the input matrix.