An analog-to-digital converter and a clock generation circuit thereof are provided. The clock generation circuit comprises cascaded clock generation modules. The clock generation module at each stage is configured to generate a corresponding internal clock signal, and each stage of the clock generation module comprises a delay module and a logic gate module. The second input end of the N-th stage of the logic gate module is connected to the output end of the previous stage of the logic gate module, and the output end of the logic gate module is configured to output an internal clock, so that each stage of the clock generation module can generate one internal clock signal.

An analog-to-digital conversion device is provided that includes a front SAR ADC and a plurality of rear SAR ADCs. The front SAR ADC is configured to convert an analog input signal into a group of higher bits of a digital output signal in response to different time periods. Each of the rear SAR ADCs is electrically coupled to the front SAR ADC and is configured to receive the analog input signal and the corresponding group of higher bits in response to the different time periods. The rear SAR ADCs convert the analog input signal into a group of lower bits of the digital output signal corresponding to the time period of the group of higher bits.

An analog-to-digital converter, including a sample/hold circuit; a reference voltage driver; a digital-to-analog converter; a comparator; and a logic circuit, wherein the reference voltage driver includes: a first voltage supplier circuit configured to output an external supply voltage provided from outside of the analog-to-digital converter; a second voltage supplier circuit configured to output a sampled reference voltage that is obtained during a sampling phase based on control signals received from the logic circuit; and a switching driver configured to electrically connect the first voltage supplier circuit to the digital-to-analog converter during a first conversion phase after the sampling phase based on the control signals received from the logic circuit, and to electrically connect the second voltage supplier circuit to the digital-to-analog converter during a second conversion phase based on the control signals received from the logic circuit.

A confined data communication system includes a reference generation circuit operable to produce one or more analog reference signals, an analog to digital converter circuit operable to process an analog signal to produce a digital representative signal, a digital filtering circuit operable to filter the digital representative signal to produce an affect value, a data processing module operable to interpret the affect value to produce processed output data, and a processing module operable to set frequency and waveform for each of the one or more analog reference signals, set digital filtering parameters for the digital filtering circuit, set a sampling rate for the analog to digital converter circuit, and set data interpretation parameters for the data processing module.

The invention relates to a method for synchronizing a plurality of analogue-digital or digital-analogue converters (CONV_k), the converters (CONV_k) all being connected to a control unit (UC), and to a clock (CLK) that has a predefined clock period (T.sub.clk), the converters being also chained step-by-step so as to form a chain of converters, each converter (CONV_k) generating an internal synchronization signal (internal_sync_k) configured to supply a time reference on the transmission of data by the converter (CONV_k).

The method allows the synchronization of the converters to be guaranteed using a process of learning and of configuration of the converters. The method allows any line distance constraint on the synchronization signal to be overcome.

A high resolution analog to digital converter (ADC) with improved bandwidth senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. In addition, quantization noise is subtracted from the digital output signal thereby extending the operational bandwidth of the ADC. In certain examples, the operational bandwidth of the ADC extends up to 100s of kHz (e.g., 200-300 kHz), or even higher.

An apparatus as described herein may include an antenna array that receives radio frequency signals and outputs analog signals. The apparatus may also include analog to digital signal converters that convert the analog signals into digital sample streams. Also, the apparatus may include a sample buffer that buffers subsets of the digital sample streams and a beamformer that uses the digital sample streams to generate one or more beam signals. Additionally, the apparatus may include a processor that determines a spatial characteristic or a spectral characteristic for the radio frequency signals based on the subsets of the digital sample streams.

An apparatus as described herein may include an antenna array that receives radio frequency signals and outputs analog signals. The apparatus may also include analog to digital signal converters that convert the analog signals into digital sample streams. Also, the apparatus may include a sample buffer that buffers subsets of the digital sample streams and a beamformer that uses the digital sample streams to generate one or more beam signals. Additionally, the apparatus may include a processor that determines a spatial characteristic or a spectral characteristic for the radio frequency signals based on the subsets of the digital sample streams.

An integrated circuit includes a set of N unit analog-to-digital converters (ADCs) having a common architecture, and which provide an aggregate data rate. Moreover, the integrated circuit includes control logic that selects subsets of the set of N unit ADCs in order to realize sub-ADCs of different data rates that can each be an arbitrary integer multiple of an inverse of N times the aggregate data rate of the N unit ADCs. Furthermore, the control logic may dynamically select the subsets on the fly or on a frame-by-frame basis. This dynamically selection may occur at boot time and/or a runtime. Additionally, the given different data rate may correspond to one or more phases of a multi-phase clock in the integrated circuit, where the multiphase clock may include a number of phases corresponding to a number of possible subsets, and given selected subsets may not use all of the available phases.

A data acquisition system comprises a signal processing chain including an analog-to-digital converter (ADC) circuit configured to: produce a digital output from an input signal; detect a specified signal feature of the input signal; and change an operating condition of an additional circuit of the signal processing chain in response to detecting the signal feature of the input signal.