A programmable drive-sense unit (DSU) includes a drive-sense circuit operably coupled to a load, wherein the drive-sense circuit is configured to drive and simultaneously to sense the load via a single line, and produce an analog output based on the sensing the load. The programmable DSU also includes an analog to digital circuit operably coupled to the drive-sense circuit, where the analog to digital circuit is operable to generate a digital output based on the analog output and in accordance with one or more programmable operational parameters to achieve one or more of load sensing objectives associated with the sensing of the load and data processing objectives associated with the sensing of the load.

In a solid-state imaging element equipped with per-column ADCs, noise is reduced. A test signal source generates a test signal of a predetermined level. An analog-to-digital converter increases/decreases an analog signal according to an analog gain selected from among a plurality of analog gains, and converts the increased/decreased analog signal to a digital signal. An input switching section inputs, as the analog signal, either a test signal or a pixel signal to the analog-to-digital converter. A correction value calculation section obtains, on the basis of the test signal and the digital signal, a correction value for correcting an error in the selected analog gain, and outputs the correction value. A correction section corrects the digital signal according to the outputted correction value.

In a described example, a method for forming a capacitor includes: forming a capacitor first plate over a non-conductive substrate; flowing ammonia and nitrogen gas into a plasma enhanced chemical vapor deposition (PECVD) chamber containing the non-conductive substrate; stabilizing a pressure and a temperature in the PECVD chamber; turning on radio frequency high frequency (RF-HF) power to the PECVD chamber; pretreating the capacitor first plate for at least 60 seconds; depositing a capacitor dielectric on the capacitor first plate; and depositing a capacitor second plate on the capacitor dielectric.

A semiconductor device, including: a thermistor for temperature detection; a series resistor selection circuit including a series resistor group connected in series with the thermistor, the series resistor selection circuit being configured to select a series resistor from the series resistor group according to a selection signal; an analog/digital (A/D) converter that performs A/D conversion on a divided voltage obtained by dividing an internal power supply voltage between the thermistor and the selected series resistor to generate divided voltage data, and outputs the divided voltage data; and a control circuit. The control circuit, during a period of selecting the series resistor, controls the A/D converter to operate in a low bit count mode, such that the selected series resistor causes the divided voltage data to fall within a predetermined voltage range, and controls the A/D converter to operate in a high bit count mode after selecting the series resistor.

An ADC system dynamically adjusts threshold levels used to resolve PAM signal amplitudes into digital values. The ADC circuitry includes an analog front end to receive and condition the PAM signal, a low-resolution ADC to digitize the conditioned signal according to a first set of threshold values, and a high-resolution ADC to subsample the conditioned signal to generate subsampled signals. A microprocessor in communication with the low-resolution ADC and the high-resolution ADC derives a statistical value from the subsampled signals, determines an updated set of threshold values, and dynamically replaces the first set of threshold values for the low-resolution ADC with the updated set of threshold values.

Techniques and apparatus for output common-mode control of dynamic amplifiers, as well as analog-to-digital converters (ADCs) and other circuits implemented with such dynamic amplifiers. One example amplifier circuit includes a dynamic amplifier and a current source. The dynamic amplifier generally includes differential inputs, differential outputs, transconductance elements coupled to the differential inputs, a first set of capacitive elements coupled to the differential outputs, and a control input for controlling a time length of amplification for the dynamic amplifier. The current source is configured to generate an output current such that portions of the output current are selectively applied to the differential outputs of the dynamic amplifier during at least a portion of the time length of amplification.

A motor drive control device capable of reliably acquiring currents of coils of two phases by a one-shunt current detection system is provided. The motor drive control device includes: a motor drive unit including an inverter circuit; a single current detection circuit connected to a direct current line of the inverter circuit, and detecting a current flowing through the direct current line; and a control circuit unit performing analog-to-digital conversion processing of the current to take in the current, and performing PWM control on the motor drive unit. The control circuit unit acquires, from the current detection circuit, a detection result of a first current and a second current being currents of coils of two phases among coils of three phases in a half cycle of one PWM cycle, and, when the A/D conversion processing of at least one of the first current and the second current is unsuccessful, reacquires, in the same PWM cycle or a next or subsequent PWM cycle, a detection result of only the current unsuccessful in the A/D conversion processing, and performs the A/D conversion processing of the reacquired detection current.

A motor drive control device capable of reliably acquiring currents of coils of two phases by a one-shunt current detection system is provided. The motor drive control device includes: a motor drive unit including an inverter circuit; a single current detection circuit connected to a direct current line of the inverter circuit, and detecting a current flowing through the direct current line; and a control circuit unit performing analog-to-digital conversion processing of the current to take in the current, and performing PWM control on the motor drive unit. The control circuit unit acquires, from the current detection circuit, a detection result of a first current and a second current being currents of coils of two phases among coils of three phases in a half cycle of one PWM cycle, and, when the A/D conversion processing of at least one of the first current and the second current is unsuccessful, reacquires, in the same PWM cycle or a next or subsequent PWM cycle, a detection result of only the current unsuccessful in the A/D conversion processing, and performs the A/D conversion processing of the reacquired detection current.

A method for determining an inverse impulse response of a communication channel by means of a PAM receiver comprises the following method steps: switching on the PAM receiver; if a second PAM transceiver is switched on, setting a difference between a clock frequency of the data signal and a sampling frequency of the first PAM transceiver; comparing a symbol that is output by the interpreter with a state that is supplied to the interpreter, and outputting an error value, wherein in each case a symbol associated with a sampling clock is compared with a state associated with the same sampling clock; adapting m filter coefficients of the equalizer to minimize error values; repeating the third method step and the fourth method step until an error limit value is reached.

A merging unit including one or more input interfaces for receiving a plurality of input signals wherein one or more voltages and/or one or more currents measured by a plurality of measurement devices, digital processing means and one or more output interfaces for outputting an output signal. The digital processing means are configured to high-pass filter, using one or more digital filters, at least one of the plurality of input signals for lowering a time constant associated with the at least one of the one or more input signals to match a target time constant or for raising a high-pass cut-off frequency associated with the at least one of the one or more input signals to match a target high-pass cut-off frequency and to merge, following the high-pass filtering, the plurality of input signals into the output signal having a pre-defined output format.