A test method is provided to test a semiconductor integrated circuit including an analog-to-digital converter and/or a digital-to-analog converter. An analog test signal having a test pattern is generated using an analog test signal generator or a digital test signal having the test pattern using a digital test signal generator. An analog output signal corresponding to the test pattern is generated by applying, as a digital input signal, the digital test signal having the test pattern to a digital-to-analog converter responsive to generation of the digital test signal. A digital output signal corresponding to the test pattern is generated by applying, as an analog input signal, the analog test signal having the test pattern or the analog output signal corresponding to the test pattern to an analog-to-digital converter. A normality of the semiconductor integrated circuit is determined based on the digital output signal corresponding to the test pattern.

A phase-shifted sampling module for sampling a signal is described. The phase-shifted sampling module includes a primary sampler module, an ADC module, and an equalization module. The primary sampler module includes an analog signal input, a first signal path, and a second signal path. The equalization module includes a primary sampler equalizer sub-module. The primary sampler equalizer sub-module is configured to compensate low-frequency mismatches between the first signal path and the second signal path. Further, a method for determining filter coefficients of an equalization module of a phase-shifted sampling module is described.

An analog-to-digital converter (ADC) circuit comprises one or more most-significant-bit (MSB) capacitors having first ends connected to a voltage comparator and one or more least-significant-bit (LSB) capacitors having first ends connected to the comparator. The circuit further comprises a first switching circuit for each MSB capacitor, configured to selectively connect the second end of the respective MSB capacitor to (a) an input voltage, for sampling, (b) a ground reference, during portions of a conversion phase, and (c) a first conversion reference voltage, for other portions of the conversion phase. The circuit still further comprises a second switch circuit, for each LSB capacitor, configured to selectively connect the second end of the respective LSB capacitor between (d) the ground reference, during portions of the conversion phase, and (e) a second conversion reference voltage, for other portions of the conversion phase, the second conversion reference voltage differing from the first.

An electronic device and method of operating the electronic device are provided. The electronic device includes a housing, a first connector configured to be exposed to outside of the housing and include a first number of pins, a second connector configured to be exposed to the outside of the housing and include a second number of pins, and a circuit configured to provide an electrical connection between the first number of pins and the second number of pins, wherein the first number is different from the second number, and wherein, when the first connector is connected with a first external electronic device and the second connector is connected with a second external electronic device, the circuit is configured to receive analog identification (ID) information through at least one pin among the first number of pins, and generate digital ID information at least partially based on the analog ID information so as to provide the digital ID information to at least one of the second number of pins.

An electronic device and method of operating the electronic device are provided. The electronic device includes a housing, a first connector configured to be exposed to outside of the housing and include a first number of pins, a second connector configured to be exposed to the outside of the housing and include a second number of pins, and a circuit configured to provide an electrical connection between the first number of pins and the second number of pins, wherein the first number is different from the second number, and wherein, when the first connector is connected with a first external electronic device and the second connector is connected with a second external electronic device, the circuit is configured to receive analog identification (ID) information through at least one pin among the first number of pins, and generate digital ID information at least partially based on the analog ID information so as to provide the digital ID information to at least one of the second number of pins.

The embodiments of the present disclosure are for a signal processing circuit. The signal processing circuit includes an analog circuit. The analog circuit is used for processing an initial signal it receives. The initial signal includes a target signal and a noise signal. The analog circuit includes a first processing circuit and a second processing circuit. The first processing circuit is used to increase a ratio of the target signal to the noise signal, and output a first processed signal. The second processing circuit is used to amplify the first processed signal. A gain multiple of the second processing circuit to the first processed signal varies with a frequency of the first processed signal. The first processing circuit includes a common mode signal suppression circuit used to suppress a common mode signal in the initial signal, a lowpass filter circuit, and a high-pass filter circuit.

A plasma deposition system comprising a wafer platform, a second electrode, a first electrode, a first high voltage pulser, and a second high voltage pulser. In some embodiments, the second electrode may be disposed proximate with the wafer platform. In some embodiments, the second electrode can include a disc shape with a central aperture; a central axis, an aperture diameter, and an outer diameter. In some embodiments, the first electrode may be disposed proximate with the wafer platform and within the central aperture of the second electrode. In some embodiments, the first electrode can include a disc shape, a central axis, and an outer diameter. In some embodiments, the first high voltage pulser can be electrically coupled with the first electrode. In some embodiments, the second high voltage pulser can be electrically coupled with the second electrode.

A plasma deposition system comprising a wafer platform, a second electrode, a first electrode, a first high voltage pulser, and a second high voltage pulser. In some embodiments, the second electrode may be disposed proximate with the wafer platform. In some embodiments, the second electrode can include a disc shape with a central aperture; a central axis, an aperture diameter, and an outer diameter. In some embodiments, the first electrode may be disposed proximate with the wafer platform and within the central aperture of the second electrode. In some embodiments, the first electrode can include a disc shape, a central axis, and an outer diameter. In some embodiments, the first high voltage pulser can be electrically coupled with the first electrode. In some embodiments, the second high voltage pulser can be electrically coupled with the second electrode.

A photoelectric conversion apparatus includes a pixel which includes a photoelectric conversion element; a signal line connected with the pixel; a voltage-current conversion unit configured to convert a voltage signal of the signal line into current; and a conversion unit that includes an oversampling type analog-to-digital conversion circuit that converts the current outputted from the voltage-current conversion unit into digital signals. The voltage-current conversion unit converts the voltage signal of the signal line into the current without sampling and holding and outputs the converted current to the conversion unit.

A microphone system includes: a microphone including a microphone output terminal and a microphone GND terminal, the microphone being configured to output, as an input sound signal, a voltage signal exhibiting a change in voltage between the microphone output terminal and the microphone GND terminal depending on an input sound; an A/D converting unit mounted on a first circuit board and configured to perform digital conversion on the input sound signal that is input; and a power supply circuit mounted on a second circuit board connected to the first circuit board via a pair of power supply lines, and configured to feed DC power to the A/D converting unit via the pair of power supply lines. The microphone outputs the input sound signal to the A/D converting unit via a pair of first signal lines different from the pair of power supply lines.