A ultra-high speed DAC apparatus (e.g., with a full sampling frequency not less than 20 GHz) may include one or more digital pre-coders and DAC modules. Each DAC module may include multiple current-mode DAC systems and a first power combiner. The gate length of transistors within each DAC module may be between 6 and 40 nm. Each current-mode DAC system includes a transmission line (e.g., 40 to 80 microns long) coupled to multiple interleaving sub-DAC systems (within the current-mode DAC systems) and the first power combiner. The first power combiner combines, without interleaving, analog signals that have been interleaved within the current-mode DAC systems. The impedance of the first power combiner matches the impedance of each of the current-mode DAC systems and a load of the first power combiner. A second power combiner combines, without interleaving, analog signals from the DAC modules.

In one embodiment, an apparatus includes: a digital-to-analog converter (DAC) circuit having a digital portion to receive a digital value and an analog portion to generate an analog voltage based on the digital value; and a refresh circuit coupled to the DAC circuit to clock gate provision of a first clock signal to the DAC circuit when the digital portion is inactive.

A novel and useful controlled quantum shift register for transporting particles from one quantum dot to another in a quantum structure. The shift register incorporates a succession of qdots with tunneling paths and control gates. Applying appropriate control signals to the control gates, a particle or a split quantum state is made to travel along the shift register. The shift register also includes ancillary double interaction where two pairs of quantum dots provide an ancillary function where the quantum state of one pair is replicated in the second pair. The shift register also provides bifurcation where an access path is split into two or more paths. Depending on the control pulse signals applied, quantum dots are extended into multiple paths. Control of the shift register is provided by electric control pulses. An optional auxiliary magnetic field provides additional control of the shift register.

A method of operating a display device comprising a drive circuit is disclosed. The drive circuit comprises a plurality of single grey-level channels, each comprising an input (412, 422), an output (418, 428) and a signal processor connected between the input and output. Each signal processor comprises a digital-to-analog converter (414, 424) and an operational amplifier (416, 426) having a voltage offset. The method comprises: converting a digital signal received at the input (412, 422) into an analog voltage (410, 420) at the output (418, 428) using each respective signal processor; switching between the analog voltage (410, 420) of each single grey-level channel using a switching circuit (430); receiving and analysing the analog voltages (410, 420) in a calibration subsystem (440), and individually compensating for the voltage offset of each op-amp (416, 426) based on the received analog voltage (410, 420) for that grey-level channel using the calibration subsystem (440).

In one embodiment, an apparatus includes: a digital-to-analog converter (DAC) circuit having a digital portion to receive a digital value and an analog portion to generate an analog voltage based on the digital value; and a refresh circuit coupled to the DAC circuit to clock gate provision of a first clock signal to the DAC circuit when the digital portion is inactive.

In one embodiment, an apparatus includes: a digital-to-analog converter (DAC) circuit having a digital portion to receive a digital value and an analog portion to generate an analog voltage based on the digital value; and a refresh circuit coupled to the DAC circuit to clock gate provision of a first clock signal to the DAC circuit when the digital portion is inactive.

A variable gain phase shifter includes an I/Q generator and a vector summation circuit. The I/Q generator generates phase signals based on an input signal. The vector summation circuit adjusts magnitudes and directions of first, second, third and fourth in-phase vectors and first, second, third and fourth quadrature vectors, and generates an output signal by summing the in-phase vectors and the quadrature vectors, based on the phase signals, selection signals and current control signals. The vector summation circuit includes first, second, third and fourth vector summation cells and first, second, third and fourth current control circuits. The first and second vector summation cells adjust the directions of the first and second in-phase vectors and the first and second quadrature vectors. The third and fourth vector summation cells adjust the directions of the third and fourth in-phase vectors and the third and fourth quadrature vectors. The first and second current control circuits are connected to the first and second vector summation cells, and adjust an amount of a first current and an amount of a second current. The third and fourth current control circuits are connected to the third and fourth vector summation cells, and adjust an amount of a third current and an amount of a fourth current.

A variable gain phase shifter includes an I/Q generator and a vector summation circuit. The I/Q generator generates phase signals based on an input signal. The vector summation circuit adjusts magnitudes and directions of first, second, third and fourth in-phase vectors and first, second, third and fourth quadrature vectors, and generates an output signal by summing the in-phase vectors and the quadrature vectors, based on the phase signals, selection signals and current control signals. The vector summation circuit includes first, second, third and fourth vector summation cells and first, second, third and fourth current control circuits. The first and second vector summation cells adjust the directions of the first and second in-phase vectors and the first and second quadrature vectors. The third and fourth vector summation cells adjust the directions of the third and fourth in-phase vectors and the third and fourth quadrature vectors. The first and second current control circuits are connected to the first and second vector summation cells, and adjust an amount of a first current and an amount of a second current. The third and fourth current control circuits are connected to the third and fourth vector summation cells, and adjust an amount of a third current and an amount of a fourth current.

Multipliers and Multiply-Accumulate (MAC) circuits are fundamental building blocks in signal processing, including in emerging applications such as machine learning (ML) and artificial intelligence (AI) that predominantly utilize digital-mode multipliers and MACs. Generally, digital multipliers and MACs can operate at high speed with high resolution, and synchronously. As the resolution and speed of digital multipliers and MACs increase, generally the dynamic power consumption and chip size of digital implementations increases substantially that makes them impractical for some ML and AI segments, including in portable, mobile, near edge, or near sensor applications. The multipliers and MACs utilizing the disclosed current mode data-converters are manufacturable in main-stream digital CMOS process, and they can have medium to high resolutions, capable of low power consumptions, having low sensitivity to power supply and temperature variations, as well as operating asynchronously, which makes them suitable for high-volume, low cost, and low power ML and AI applications.

Multipliers and Multiply-Accumulate (MAC) circuits are fundamental building blocks in signal processing, including in emerging applications such as machine learning (ML) and artificial intelligence (AI) that predominantly utilize digital-mode multipliers and MACs. Generally, digital multipliers and MACs can operate at high speed with high resolution, and synchronously. As the resolution and speed of digital multipliers and MACs increase, generally the dynamic power consumption and chip size of digital implementations increases substantially that makes them impractical for some ML and AI segments, including in portable, mobile, near edge, or near sensor applications. The multipliers and MACs utilizing the disclosed current mode data-converters are manufacturable in main-stream digital CMOS process, and they can have medium to high resolutions, capable of low power consumptions, having low sensitivity to power supply and temperature variations, as well as operating asynchronously, which makes them suitable for high-volume, low cost, and low power ML and AI applications.