Digital-to-analog converter (DAC) circuitry for providing currents at electrodes of an Implantable Pulse Generator (IPG) is disclosed. The DAC circuitry includes at least one PDAC for sourcing current to the electrodes, and at least one NDAC for sinking current from the electrodes. The PDACs are powered with power supplies VH (the compliance voltage) and Vssh in a high power domain, and the NDACs are powered with power supplies Vcc and ground in a low power domain. VH may change during IPG operation, and Vssh preferably also changes with a fixed difference with respect to VH. Digital control signals to the PDACs are formed (and possibly converted into) the high power domain, and transistors used to build the PDACs are biased in the high power domain, and thus may also change with VH. This permits transistors in the PDACs and NDACs to be made from normal low-voltage logic transistors.

An H-bridge integrated laser driver optimizes power dissipation, impedance matching, low-swing and high-swing reliability for electro-absorption modulated laser (EML) and directly modulated laser diode (DML) applications. The laser driver includes a retimer for converting low-speed parallel data to a high-speed serial bit stream and to an inverted representation of the high-speed parallel bit stream, an M-bit PMOS DAC configured to receive a first buffered bit stream, an N-bit NMOS DAC configured to receive a second buffered bit stream substantially synchronized with the first buffered bit stream. A protective device is coupled between the M-bit DAC and the N-bit DAC. A first DC level-shifting predriver array is coupled between the retimer and the M-bit DAC to receive the high-speed parallel bit stream and the inverted high-speed parallel bit stream, and a second DC level-shifting predriver array is coupled between the retimer and the N-bit DAC to receive the high-speed parallel bit stream and the inverted high-speed parallel bit stream. An impedance matching module is coupled to an output of the protective device. The laser driver may be integrated on a CMOS communication chip.

An H-bridge integrated laser driver optimizes power dissipation, impedance matching, low-swing and high-swing reliability for electro-absorption modulated laser (EML) and directly modulated laser diode (DML) applications. The laser driver includes a retimer for converting low-speed parallel data to a high-speed serial bit stream and to an inverted representation of the high-speed parallel bit stream, an M-bit PMOS DAC configured to receive a first buffered bit stream, an N-bit NMOS DAC configured to receive a second buffered bit stream substantially synchronized with the first buffered bit stream. A protective device is coupled between the M-bit DAC and the N-bit DAC. A first DC level-shifting predriver array is coupled between the retimer and the M-bit DAC to receive the high-speed parallel bit stream and the inverted high-speed parallel bit stream, and a second DC level-shifting predriver array is coupled between the retimer and the N-bit DAC to receive the high-speed parallel bit stream and the inverted high-speed parallel bit stream. An impedance matching module is coupled to an output of the protective device. The laser driver may be integrated on a CMOS communication chip.

Multipliers and Multiply-Accumulate (MAC) circuits are fundamental building blocks in signal processing, including in emerging applications such as machine learning (ML) and artificial intelligence (AI) that predominantly utilize digital-mode multipliers and MACs. Generally, digital multipliers and MACs can operate at high speed with high resolution, and synchronously. As the resolution and speed of digital multipliers and MACs increase, generally the dynamic power consumption and chip size of digital implementations increases substantially that makes them impractical for some ML and AI segments, including in portable, mobile, near edge, or near sensor applications. The multipliers and MACs utilizing the disclosed current mode data-converters are manufacturable in main-stream digital CMOS process, and they can have medium to high resolutions, capable of low power consumptions, having low sensitivity to power supply and temperature variations, as well as operating asynchronously, which makes them suitable for high-volume, low cost, and low power ML and AI applications.

Apparatus and associated methods relate to unit circuits that having a number of capacitors and/or buffers controlled by two different control signals, capacitors and/or buffers that receiving, through routing, a same control signal from a control circuit are physically placed adjacent without crossing routings that connects capacitors and/or buffers controlled by a different control signal. In an illustrative example, a first capacitor may be configured to receive a first control signal through an inverting buffer, and a second capacitor may be configured to receive the first control signal through a non-inverting buffer, the inverting buffer and the non-inverting buffer may be provided by an integrated buffer structure. By arranging the physical positions of the capacitors and/or buffers, wire capacitances of the unit circuit may be advantageously reduced.

Systems, methods, and circuitries are provided for generating a power amplifier supply voltage based on a target envelope signal for a radio frequency (RF) transmit signal. An envelope tracking system includes a first selector circuitry and predistortion circuitry. The first selector circuitry is disposed in a selector module and is configured to input a plurality of voltages conducted on a first plurality of power lanes, wherein the first plurality of power lanes is part of a power distribution network; select a voltage from the plurality of voltages based on the target envelope signal; and provide the selected voltage to a supply lane connected to an input of the power amplifier that amplifies the RF transmit signal. The predistortion circuitry is configured to modify the RF transmit signal based on a selected power lane of the first plurality of power lanes that conducts the selected voltage.

Systems, methods, and circuitries are provided for generating a power amplifier supply voltage based on a target envelope signal for a radio frequency (RF) transmit signal. An envelope tracking system includes a first selector circuitry and predistortion circuitry. The first selector circuitry is disposed in a selector module and is configured to input a plurality of voltages conducted on a first plurality of power lanes, wherein the first plurality of power lanes is part of a power distribution network; select a voltage from the plurality of voltages based on the target envelope signal; and provide the selected voltage to a supply lane connected to an input of the power amplifier that amplifies the RF transmit signal. The predistortion circuitry is configured to modify the RF transmit signal based on a selected power lane of the first plurality of power lanes that conducts the selected voltage.

An apparatus is provided which comprises: a frequency locked loop (FLL) comprising an oscillator including a plurality of delay stages, wherein an output of each delay stage is counted to determine a frequency of the FLL; and one or more circuitries coupled to the FLL to adjust a power supply to the FLL according to the determined frequency of the FLL.

The differential difference amplifier circuit includes a differential input stage circuit, a loading stage circuit coupled to the differential input stage circuit, and an output stage circuit coupled to the loading stage circuit. The output stage circuit is configured to generate an output signal. The differential input stage circuit includes a first differential pair having a first transconductance and a second differential pair having a second transconductance. The first differential pair is biased by a first current source and receives a first input signal and the output signal. The second differential pair is biased by a second current source and receives a second input signal and the output signal. At least one of the first transconductance and the second transconductance is adjusted according to the image data.

Disclosed examples include a segmented DAC circuit, including an R-2R resistor DAC to convert a first subword to a first analog output signal, an interpolation DAC to offset the first analog output signal based on an N-bit digital interpolation code signal to provide the analog output signal, and a Sigma Delta modulator to modulate a modulator code to provide the N-bit digital interpolation code signal that represents a value of second and third subwords.