A sensor device includes at least one sensor, a digital signal processor and an amplifier. The at least one sensor is configured to measure a variable physical quantity and provide a raw sensor signal at an output of the at least one sensor. The digital signal processor is configured to preprocess the raw sensor signal output by the at least one sensor into a sensor signal and to further process the sensor signal into a pulse-width-modulated output signal having a duty cycle that is dependent on the measured quantity using a plurality of device-specific correction parameters stored in a memory to convert the sensor signal into the pulse-width modulated output signal. The amplifier is configured to convert the pulse-width modulated output signal into an analog voltage or current signal.

Described are apparatuses and methods of current balancing, current sensing and phase balancing, offset cancellation, digital to analog current converter with monotonic output using binary coded input (without binary to thermometer decoder), compensator for a voltage regulator (VR), etc. In one example, apparatus comprises: a plurality of inductors coupled to a capacitor and a load; a plurality of bridges, each of which is coupled to a corresponding inductor from the plurality of inductors; and a plurality of current sensors, each of which is coupled to a bridge to sense current through a transistor of the bridge.

Described are apparatuses and methods of current balancing, current sensing and phase balancing, offset cancellation, digital to analog current converter with monotonic output using binary coded input (without binary to thermometer decoder), compensator for a voltage regulator (VR), etc. In one example, apparatus comprises: a plurality of inductors coupled to a capacitor and a load; a plurality of bridges, each of which is coupled to a corresponding inductor from the plurality of inductors; and a plurality of current sensors, each of which is coupled to a bridge to sense current through a transistor of the bridge.

Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a braided pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures. Galvanic connections between DACs and/or with target devices are disclosed, as well as inductive connections.

A radio frequency transmitter including two digital to analog converter circuits. The two radio frequency digital to analog converter circuits are configured to operate independently or operating in unison. Operating independently includes each radio frequency digital to analog converter circuit of the two radio frequency digital to analog converter circuits receiving separate baseband signals and separate local oscillation inputs. Operating in unison includes both of the two radio frequency digital to analog converter circuits receiving a single baseband signal and a single local oscillation input. The two radio frequency digital to analog converter circuits are configured to change between operating independently and operating in unison.

A radio frequency transmitter including two digital to analog converter circuits. The two radio frequency digital to analog converter circuits are configured to operate independently or operating in unison. Operating independently includes each radio frequency digital to analog converter circuit of the two radio frequency digital to analog converter circuits receiving separate baseband signals and separate local oscillation inputs. Operating in unison includes both of the two radio frequency digital to analog converter circuits receiving a single baseband signal and a single local oscillation input. The two radio frequency digital to analog converter circuits are configured to change between operating independently and operating in unison.

An apparatus includes a slicer circuit, a frequency acquisition circuit, a phase acquisition circuit and an oscillator circuit. The slicer circuit may be configured to (i) generate an output signal by slicing a data signal in response to a clock signal and (ii) generate a crossing signal in response to the data signal and the clock signal. The frequency acquisition circuit may be configured to generate a first control signal and a second control signal in response to the data signal and the clock signal. The phase acquisition circuit may be configured to generate a third control signal in response to the first control signal and the data crossing signal. The oscillator circuit may be configured to generate the clock signal in response to the second control signal and the third control signal. The second control signal may shift an adjustable frequency range of the clock signal.

An apparatus includes a slicer circuit, a frequency acquisition circuit, a phase acquisition circuit and an oscillator circuit. The slicer circuit may be configured to (i) generate an output signal by slicing a data signal in response to a clock signal and (ii) generate a crossing signal in response to the data signal and the clock signal. The frequency acquisition circuit may be configured to generate a first control signal and a second control signal in response to the data signal and the clock signal. The phase acquisition circuit may be configured to generate a third control signal in response to the first control signal and the data crossing signal. The oscillator circuit may be configured to generate the clock signal in response to the second control signal and the third control signal. The second control signal may shift an adjustable frequency range of the clock signal.

The method according to the invention and the device according to the invention for receiving at least one high-frequency signal (x(t)) using parallel and undersampled baseband signal processing generate a plurality of filtered signals (y.sub.1(t), y.sub.2(t), . . . , y.sub.N(t)) through parallel filtering of the high-frequency signal (x(t)), wherein each individual filtering is performed in each case by means of a different filter frequency response. An associated digitized filtered signal (y.sub.1(n.Math.T.sub.A), y.sub.2(n.Math.T.sub.A), . . . , y.sub.N(n.Math.T.sub.A)) is then generated in each case for each filtered signal (y.sub.1(t), y.sub.2(t), . . . , y.sub.N(t)) through analog-to-digital conversion of the respective filtered signal (y.sub.1(t), y.sub.2(t), . . . , y.sub.N(t)), wherein each analog-to-digital conversion is performed in each case by means of undersampling. Finally, the signal components (x.sub.1(n.Math.T.sub.A), . . . , x.sub.M(n.Math.T.sub.A); X.sub.1(k.Math.f), . . . , X.sub.M(k.Math.f)) of the high-frequency signal (x(t)) in the digital baseband are determined by means of equalization of baseband signal components (l.sub.1(n.Math.T), l.sub.2(n.Math.T.sub.A), . . . , l.sub.N(n.Math.T.sub.A); L.sub.1(k.Math.f), L.sub.2(k.Math.f), . . . , L.sub.N(k.Math.f)) of the associated digitized filtered signals (y.sub.1(t), y.sub.2(t), . . . , y.sub.N(t)). A complementary method and device for transmitting at least one high-frequency signal (z(t)) using parallel and undersampled baseband signal processing, and also a system for transmitting at least one high-frequency signal using parallel and undersampled baseband signaling processing are also encompassed by the invention.

A method of arranging components in an integrated circuit includes providing two or more circuit cells of a first type and providing two or more circuit cells of a second type. The circuit cells of the first type are configured to operate in conjunction with the circuit cells of the second type. The method further includes arranging the circuit cells of the first and second types in an alternating pattern such that each circuit cell of the first type is adjacent to at least one circuit cell of the second type. The alternating pattern may be an array of rows and columns and may include a repeating pattern of one first type cell and one second type cell in each of the columns. The alternating pattern may include a repeating pattern of one cell of the first type and two cells of the second type in each of the columns.