A method of calibrating a delay generation circuit and the corresponding circuit.

A method of calibrating a delay generation circuit and the corresponding circuit.

In an example, a circuit includes a first comparator, a second comparator, a pulse counter, a processor, a first ADC, and a second ADC. The first comparator has a first input coupled to a first node, a second input, and an output. The second comparator has a first input coupled to a second node, a second input, and an output. A first DAC is coupled to the second input of the first comparator. A second DAC is coupled to the second input of the second comparator. The pulse counter has a first input coupled to the output of the first comparator and a second input coupled to the output of the second comparator. The first ADC has an input coupled to the first node and an output coupled to the processor. The second ADC has an input coupled to the second node and an output coupled to the processor.

In an example, a circuit includes a first comparator, a second comparator, a pulse counter, a processor, a first ADC, and a second ADC. The first comparator has a first input coupled to a first node, a second input, and an output. The second comparator has a first input coupled to a second node, a second input, and an output. A first DAC is coupled to the second input of the first comparator. A second DAC is coupled to the second input of the second comparator. The pulse counter has a first input coupled to the output of the first comparator and a second input coupled to the output of the second comparator. The first ADC has an input coupled to the first node and an output coupled to the processor. The second ADC has an input coupled to the second node and an output coupled to the processor.

A digital-to-analog converter (DAC) for an audio system in a media device, such as a portable media device or smart phone, may be operated to turn off portions of the DAC to reduce power consumption. Segments of a segment-able DAC may be powered off when the output level of the DAC is lower than the full scale output of the DAC. For example, DAC elements within a finite impulse response (FIR) DAC may be turned off when a desired output level can be obtained with less than all DAC elements of the FIR DAC.

An analog-to-digital converter (ADC) is provided. The ADC may include an input terminal configured to receive input signals, a digital-to-analog converter (DAC), a first switch configured to control a connection between the DAC and the input terminal, a comparator, a second switch configured to control a connection between the DAC and the comparator, and a controller configured to control the first switch, the second switch, the DAC and the comparator.

The n-bit decoder circuit includes 2.sup.n base circuits each outputting, as the output signal OA, 0, 1 or the input signal IA depending on setting of selection signals S<1:0>; and the (n1)-bit decoder circuit. The (n1)-bit decoder circuit includes 2.sup.(n-1) base circuits and an (n2)-bit decoder circuit in cases of n3, and includes the 1-bit decoder circuit in cases of n=2. The 1-bit decoder circuit outputs 00 in cases of the binary input BIN<0>=0 and outputs 01 in cases of the binary input BIN<0>=1 as thermometer outputs THM(1)<1:0>.

The n-bit decoder circuit includes 2.sup.n base circuits each outputting, as the output signal OA, 0, 1 or the input signal IA depending on setting of selection signals S<1:0>; and the (n1)-bit decoder circuit. The (n1)-bit decoder circuit includes 2.sup.(n-1) base circuits and an (n2)-bit decoder circuit in cases of n3, and includes the 1-bit decoder circuit in cases of n=2. The 1-bit decoder circuit outputs 00 in cases of the binary input BIN<0>=0 and outputs 01 in cases of the binary input BIN<0>=1 as thermometer outputs THM(1)<1:0>.

A signal processing device includes an A-D converter and a controller. The A-D converter converts an analog signal to a digital signal in which portions where the amplitude exceeds a predetermined range are clipped. A counter of the controller calculates, for the digital signal, a number of clipped samples for each predetermined number of period samples. A frequency converter performs frequency conversion of the digital signal. An LPF removes high frequency components of the digital signal. A rate converter converts a sampling rate of the A-D converter. A digital amplifier amplifies and outputs the digital signal. An amplification factor adjuster multiplies a preset amplification factor of the digital amplifier by an amplification factor adjustment coefficient based on a ratio of the number of regular samples to the number of period samples, to adjust the amplification factor.

A signal processing device includes an A-D converter and a controller. The A-D converter converts an analog signal to a digital signal in which portions where the amplitude exceeds a predetermined range are clipped. A counter of the controller calculates, for the digital signal, a number of clipped samples for each predetermined number of period samples. A frequency converter performs frequency conversion of the digital signal. An LPF removes high frequency components of the digital signal. A rate converter converts a sampling rate of the A-D converter. A digital amplifier amplifies and outputs the digital signal. An amplification factor adjuster multiplies a preset amplification factor of the digital amplifier by an amplification factor adjustment coefficient based on a ratio of the number of regular samples to the number of period samples, to adjust the amplification factor.