Patent classifications
H03M1/66
Systems and Methods for Multi-Phase Clock Generation
Systems and methods are provided for a clock generator is configured to generate N clock signals evenly spaced by phase. A clock generator includes a poly phase filter configured to utilize a differential clock signal to generate N intermediate signals, the intermediate signals being spaced approximately 360/N degrees apart in phase. A phase error corrector is configured to receive the intermediate signals and to generate N clock output signals, where a phase error is a measure of a difference in phase between consecutive ones of the clock output signals from 360/N degrees, the phase error corrector being configured to reduce phase error among the clock output signals based on a feedback signal. A phase error detection circuit is configured to receive the clock output signals and to generate the feedback signal based on detected phase errors among the clock output signals.
Systems and Methods for Multi-Phase Clock Generation
Systems and methods are provided for a clock generator is configured to generate N clock signals evenly spaced by phase. A clock generator includes a poly phase filter configured to utilize a differential clock signal to generate N intermediate signals, the intermediate signals being spaced approximately 360/N degrees apart in phase. A phase error corrector is configured to receive the intermediate signals and to generate N clock output signals, where a phase error is a measure of a difference in phase between consecutive ones of the clock output signals from 360/N degrees, the phase error corrector being configured to reduce phase error among the clock output signals based on a feedback signal. A phase error detection circuit is configured to receive the clock output signals and to generate the feedback signal based on detected phase errors among the clock output signals.
WIRING STRUCTURE FOR AUDIO SIGNAL CONVERSION APPARATUS FOR IMPROVING CROSS-TALK, AND AUDIO SIGNAL CONVERSION APPARATUS
The embodiments provide an apparatus for converting an audio signal, in which a left channel line and a right channel line connected to an amplification unit of an audio signal converting apparatus are covered with the ground and connected to a chassis of the audio signal converting apparatus, and a digital signal line and an analog signal line are disposed to be spaced apart from a substrate to improve crosstalk and remove noise.
WIRING STRUCTURE FOR AUDIO SIGNAL CONVERSION APPARATUS FOR IMPROVING CROSS-TALK, AND AUDIO SIGNAL CONVERSION APPARATUS
The embodiments provide an apparatus for converting an audio signal, in which a left channel line and a right channel line connected to an amplification unit of an audio signal converting apparatus are covered with the ground and connected to a chassis of the audio signal converting apparatus, and a digital signal line and an analog signal line are disposed to be spaced apart from a substrate to improve crosstalk and remove noise.
Closed-loop digital compensation scheme
Resistor mismatch may be digitally compensated based on a known resistor mismatch, power supply information, and/or other operating parameters of the amplifier. The digital compensation may be applied to the digital input signal before conversion for processing and amplification in the analog domain. An amplifier with digital compensation for resistor mismatch may be used in a class-D amplifier with a closed loop and feedforward feedback. A class-D or other amplifier with digital compensation may be integrated with electronic devices such as mobile phones.
Signed-RFDAC architectures enabling wideband and efficient 5G transmitters
A radio frequency digital-to-analog converter (RFDAC) circuit includes an RFDAC array circuit including an array of cells arranged into a plurality of segments. Each segment of the plurality of segments is configured to process input data signals. The RFDAC array circuit is configured to process an input data based on activating a set of segments of the plurality of segments, forming a set of active segments, and when the sign of the input data is changed, deactivate a partially active segment of the set of active segments and activate a sign change segment within the RFDAC array circuit. The sign change segment includes a segment within the plurality of segments of the RFDAC array circuit that is different from the set of active segments.
Harmonic compensation device
Disclosed is a harmonic compensation device capable of effectively reducing the harmonic distortion of an analog output signal. The harmonic compensation device includes a harmonic compensator, a mixer, a digital-to-analog converter, and an analog output circuit. The harmonic compensator is configured to generate a digital compensation signal according to a digital input signal, in which the digital compensation signal includes the harmonic components of the digital input signal. The mixer is configured to generate a digital output signal according to the digital input signal and the digital compensation signal. The digital-to-analog converter is configured to generate an analog input signal according to the digital output signal. The analog output circuit is configured to generate an analog output signal according to the analog input signal.
Harmonic compensation device
Disclosed is a harmonic compensation device capable of effectively reducing the harmonic distortion of an analog output signal. The harmonic compensation device includes a harmonic compensator, a mixer, a digital-to-analog converter, and an analog output circuit. The harmonic compensator is configured to generate a digital compensation signal according to a digital input signal, in which the digital compensation signal includes the harmonic components of the digital input signal. The mixer is configured to generate a digital output signal according to the digital input signal and the digital compensation signal. The digital-to-analog converter is configured to generate an analog input signal according to the digital output signal. The analog output circuit is configured to generate an analog output signal according to the analog input signal.
Ripple monitoring
A ripple monitoring circuit may generate information indicative of a failing component in a power supply. At least one input may receive a ripple signal from the power supply that has a ripple component. A quantization circuit may repeatedly quantize the amplitude of the ripple component. A ripple amplitude statistics counter bank may count and store the number of times that different quantized amplitudes or different ranges of quantized amplitudes of the ripple component occurred. A ripple monitoring circuit may generate information about a power supply. At least one input may receive a ripple signal from the power supply that has a ripple component. A ripple measurement circuit may measure a characteristic of the ripple component. A storage circuit may store information about the measurement. A comparison circuit may compare information stored in the storage circuit with a threshold value and indicate when the stored information meets or exceeds this threshold value.
Parameter correction for cascaded signal components
Various examples are directed to systems and methods for providing correction to cascaded signal components. A correction signal may be applied to multiple signal components in a set of cascaded signal components.