Embodiments provide an audio amplifier circuit with integrated (built-in) filter (e.g., a digital-to-analog converter (DAC) filter). The audio amplifier circuit may have a non-flat (e.g., low-pass) closed loop frequency response. The audio amplifier circuit may include a low pass filter coupled between an input terminal that receives the input analog audio signal and the input of the gain stage of the amplifier. In some embodiments, additional impedance networks may be included to produce a desired low-pass filter response, such as a second order filter, a third order filter, and/or another suitable filter response. Other embodiments may be described and/or claimed.

A method and apparatus can include: audio interface pins coupled to swappable connections including a BCLK, an LRCLK, a DIN, and a DOUT; a BCLK determiner configured to identify the BCLK as the swappable connection with a highest frequency; an LRCLK determiner configured to: measure cycle lengths, compare the cycle lengths to a pre-defined multiple, identify the LRCLK as the swappable connections, and output an association between the LRCLK and one of the audio interface pins; and a mode determiner configured to identify and output a mode based on the association of the BCLK to the audio interface pins and the association of the LRCLK to the audio interface pins.

A method and apparatus can include: audio interface pins coupled to swappable connections including a BCLK, an LRCLK, a DIN, and a DOUT; a BCLK determiner configured to identify the BCLK as the swappable connection with a highest frequency; an LRCLK determiner configured to: measure cycle lengths, compare the cycle lengths to a pre-defined multiple, identify the LRCLK as the swappable connections, and output an association between the LRCLK and one of the audio interface pins; and a mode determiner configured to identify and output a mode based on the association of the BCLK to the audio interface pins and the association of the LRCLK to the audio interface pins.

Clock distribution circuitry comprising: a plurality of first buffers and second buffers, the first and second buffers being inverting buffers; and control circuitry configured to generate first, second, third and fourth control signals for bulk-voltage control of transistors of the buffers, the control circuitry configured to control at least one of the first to fourth control signals as a variable signal.

Embodiments of the present invention provide a digital-to-analog conversion circuit, where the digital-to-analog conversion circuit includes a signal amplitude detector and a digital-to-analog converter. When the signal amplitude detector detects a low signal amplitude, a first current module in the digital-to-analog converter operates normally and a second current module in the digital-to-analog converter stops operating. In addition, when stopping operating, the second current module is in a state of a third bias voltage and a fourth bias voltage that are generated by a second bias circuit. When the amplitude detector detects a high signal amplitude subsequently, the second current module resumes normal operation. After operating normally, the second current module switches back to a first bias voltage and a second bias voltage that are generated by a first bias circuit. This reduces a nonlinearity problem caused before a second current module resumes normal operation.

A digital-to-analog converter is provided. The digital-to-analog converter includes a first plurality of digital-to-analog converter cells configured to generate a first analog signal. Further, digital-to-analog converter includes a second plurality of digital-to-analog converter cells configured to generate a second analog signal. The first analog signal and the second analog signal form a differential signal pair. Further, the digital-to-analog converter includes a transmission line transformer comprising a first input node coupled to the first plurality of digital-to-analog converter cells, a second input node coupled to the second plurality of digital-to-analog converter cells, and a first output node. The transmission line transformer is configured to present a first impedance at the first and second input nodes and to present a second impedance at the first output node.

A digital-to-analog converter is provided. The digital-to-analog converter includes a first plurality of digital-to-analog converter cells configured to generate a first analog signal. Further, digital-to-analog converter includes a second plurality of digital-to-analog converter cells configured to generate a second analog signal. The first analog signal and the second analog signal form a differential signal pair. Further, the digital-to-analog converter includes a transmission line transformer comprising a first input node coupled to the first plurality of digital-to-analog converter cells, a second input node coupled to the second plurality of digital-to-analog converter cells, and a first output node. The transmission line transformer is configured to present a first impedance at the first and second input nodes and to present a second impedance at the first output node.

The present invention relates to a detector circuit (10) being part of an RFID-device, and comprising: a bias current generator circuit (20) configured to generate an output bias current that is proportional to the square of a temperature-dependent input current, a first and a second FET-devices (21, 22), at least one of the first and the second FET-devices (21, 22) is biased by means of the output bias current of the bias current generator circuit (20) so that it operates in the sub-threshold region, an incoming RF-signal is coupled into at least one of the first and the second FET-devices, a current source (18) for generating a variable threshold current, and a comparator (19) for determining, on the basis of the variable threshold current and the incoming RF-signal, whether the value of the incoming RF-signal exceeds a threshold value.

A circuit device includes a D/A converter, a comparator that compares a temperature detection voltage from a temperature sensor unit with a D/A conversion voltage from the D/A converter, and a processing circuit that executes a determination process based on a comparison result from the comparator, and obtains temperature detection data as a result of A/D conversion of the temperature detection voltage, in which, the processing circuit determines the temperature detection data so that a change in the temperature detection data at a second output timing following a first output timing with respect to the temperature detection data at the first output timing is equal to or less than kLSB.

A circuit device includes a D/A converter, a comparator that compares a temperature detection voltage from a temperature sensor unit with a D/A conversion voltage from the D/A converter, and a processing circuit that executes a determination process based on a comparison result from the comparator, and obtains temperature detection data as a result of A/D conversion of the temperature detection voltage, in which, the processing circuit determines the temperature detection data so that a change in the temperature detection data at a second output timing following a first output timing with respect to the temperature detection data at the first output timing is equal to or less than kLSB.