A multi-zone digital-to-analog device is provided with a digital-to-analog (D/A) stage having an input to accept a digital input signal with a data bandwidth of M Hertz (Hz), a clock input to accept a clock signal with a clock frequency of P Hz, and an output to supply an analog value having a bandwidth of M Hz. An upsampling stage has an input to accept the analog value and a clock input to accept the clock signal. The upsampling stage has a device bandwidth of L Hz to supply an analog output signal with a full power bandwidth of K Hz, where (P/2)=M and M<K<L. The upsampling stage supplies analog output signal images in a plurality of Nyquist zones. In one aspect, the D/A stage supplies N deinterleaved analog values having a combined bandwidth of M Hz, where N(P/2)=M.

A broadband sender system is provided. The broadband sender system comprises a radio frequency digital-to-analog converter. In this context, the radio frequency digital-to-analog converter is adapted to emit a baseband signal modulated on a carrier signal with a first intermediate frequency and a second intermediate frequency. In addition to this, the first intermediate frequency is higher than the second intermediate frequency.

According to examples, an apparatus may include an arithmetic logic unit (ALU) to apply a modification function to a digital input signal to generate a modified digital input signal, a digital-to-analog converter (DAC) to convert the modified digital input signal to an analog input signal, a crossbar array to apply an operation on the analog input signal to generate an analog output signal, and an analog-to-digital converter (ADC). The ADC may modify the analog output signal to compensate for application of the modification function to the digital input signal, may convert the modified analog output signal to a digital output signal, and may output the digital output signal.

According to examples, an apparatus may include an arithmetic logic unit (ALU) to apply a modification function to a digital input signal to generate a modified digital input signal, a digital-to-analog converter (DAC) to convert the modified digital input signal to an analog input signal, a crossbar array to apply an operation on the analog input signal to generate an analog output signal, and an analog-to-digital converter (ADC). The ADC may modify the analog output signal to compensate for application of the modification function to the digital input signal, may convert the modified analog output signal to a digital output signal, and may output the digital output signal.

A signal processing chain, such as an audio chain, produces an analog output signal from a digital input signal. The signal processing chain is operated by generating a first flag signal for the analog output signal and one or more second flag signals for the digital input signal. Each flag signal assumes a first level or a second level and is set to the first level when a signal from which the flag is generated has a value within an amplitude window. An amount the first flag signal for the analog output signal and the second flag signal for the digital input signal match each other may be calculated for issuing an alert flag which indicates an impaired operation of the signal processing chain.

A digital to analog converter circuit applied to a source driving apparatus is disclosed. The digital to analog converter circuit includes P-type transistors coupled in series, N-type transistors coupled in series and a substrate voltage control unit. The substrate voltage control unit is coupled to substrates of the P-type transistors and substrates of the N-type transistors respectively and used for controlling the substrates of the P-type transistors to have a first substrate voltage and controlling the substrates of the N-type transistors to have a second substrate voltage. The first substrate voltage is an operating voltage substituted by a specific voltage difference and the second substrate voltage is a ground voltage added by the specific voltage difference, and the operating voltage is higher than the ground voltage.

A digital to analog converter circuit applied to a source driving apparatus is disclosed. The digital to analog converter circuit includes P-type transistors coupled in series, N-type transistors coupled in series and a substrate voltage control unit. The substrate voltage control unit is coupled to substrates of the P-type transistors and substrates of the N-type transistors respectively and used for controlling the substrates of the P-type transistors to have a first substrate voltage and controlling the substrates of the N-type transistors to have a second substrate voltage. The first substrate voltage is an operating voltage substituted by a specific voltage difference and the second substrate voltage is a ground voltage added by the specific voltage difference, and the operating voltage is higher than the ground voltage.

An offset compensation circuit comprises an error signal generation block arranged for receiving an input phase and an output phase, and for generating an error signal indicative of an error between the input phase and the output phase. Means are provided for combining the error signal with an offset compensation signal, yielding an offset compensated signal. A loop filter is arranged for receiving the offset compensated signal and for outputting the output phase. An offset compensation block is arranged for receiving the output phase and for determining the offset compensation signal. The offset compensation signal comprises at least a contribution proportional to a periodic function of the output phase.

The application provides a vector quantization digital-to-analog conversion circuit, applied to an oversampling converter, characterized that the vector quantization digital-to-analog conversion circuit includes a vector quantization circuit, configured to generate a vector quantization signal, a data weighted averaging circuit, coupled to the vector quantization circuit, including a plurality of data weighted averaging sub-circuits, configured to receive the vector quantization signal to generate a plurality of data weighted averaging signals; and a digital-to-analog conversion circuit, coupled to the data weighted averaging circuit, including a plurality of digital-to-analog conversion sub-circuits, configured to receive the data weighted averaging signal to generate the analog signal.

The application provides a vector quantization digital-to-analog conversion circuit, applied to an oversampling converter, characterized that the vector quantization digital-to-analog conversion circuit includes a vector quantization circuit, configured to generate a vector quantization signal, a data weighted averaging circuit, coupled to the vector quantization circuit, including a plurality of data weighted averaging sub-circuits, configured to receive the vector quantization signal to generate a plurality of data weighted averaging signals; and a digital-to-analog conversion circuit, coupled to the data weighted averaging circuit, including a plurality of digital-to-analog conversion sub-circuits, configured to receive the data weighted averaging signal to generate the analog signal.