An apparatus for interpolating between a first and a second signal is provided. The apparatus includes a plurality of interpolation cells coupled to a common node of the apparatus. Further, the apparatus includes a control circuit configured to supply, based on a control word, respective selection signals to each of the plurality of interpolation cells. At least one of the plurality of interpolation cells is configured to couple the common node to a first potential if the first signal and the second signal are both at a first signal level, couple the common node to a second potential, which is different from the first potential, if the first signal and the second signal are both at a second signal level, which is different from the first signal level, and to decouple the common node from at least one of the first potential and the second potential if the first signal and the second signal are at different signal levels. Additionally, the at least one of the plurality of interpolation cells is configured to switch, based on a state indicated by the respective selection signal, to coupling the common node to the second potential in response to a transition of either the leading one or the trailing one of the first signal and the second signal from the first signal level to the second signal level.

A mixed signal receiver includes a first sample and hold (S/H) circuit having a first S/H input terminal to receive an analog input signal and a first S/H output terminal directly coupled to a first common node; a first data slicer having a first slicer input terminal coupled to the first common node; and a first data-driven charge coupling digital-to-analog converter (DAC) including: (i) a DAC input terminal to receive a first digital signal from a first digital output of the first data slicer, (ii) a DAC output terminal directly coupled to the first common node, (iii) a plurality of capacitor modules configured to be pre-charged during a sample phase, and (iv) logic components, wherein when the logic components toggle a voltage on the plurality of capacitor modules, charge is capacitively coupled to or from the first common node during an immediately subsequent hold phase.

A mixed signal receiver includes a first sample and hold (S/H) circuit having a first S/H input terminal to receive an analog input signal and a first S/H output terminal directly coupled to a first common node; a first data slicer having a first slicer input terminal coupled to the first common node; and a first data-driven charge coupling digital-to-analog converter (DAC) including: (i) a DAC input terminal to receive a first digital signal from a first digital output of the first data slicer, (ii) a DAC output terminal directly coupled to the first common node, (iii) a plurality of capacitor modules configured to be pre-charged during a sample phase, and (iv) logic components, wherein when the logic components toggle a voltage on the plurality of capacitor modules, charge is capacitively coupled to or from the first common node during an immediately subsequent hold phase.

A mist generator device (400) for delivering a mist to a user, the mist generator device (400) for use with a driver device (202). The mist generator device (400) comprises a housing (204) comprising a liquid chamber (218) for containing a liquid to be atomised, a sonication assembly (425) coupled to the housing (204) the sonication assembly (425) comprising an ultrasonic transducer (215), a first assembly portion (426) and a second assembly portion (428) coupled to the first assembly portion (426). At least one of the first assembly portion (426) and the second assembly portion (428) comprises a resiliently deformable section that forms a seal between the first assembly portion (426) and the second assembly portion (428) which minimises or prevents a fluid from leaking between the first assembly portion (426) and the second assembly portion (428).

A digital-to-analog converter, including an input to receive a digital signal; a first comparator configured to receive the digital signal and output a first signal based on the digital signal and a first threshold; a second comparator configured to receive the digital signal and output a second signal based on the digital signal and a second threshold, the second threshold different from the first threshold; and an integrator configured to receive the first signal and the second signal and integrate the first signal and the second signal into an analog signal that represents the digital signal.

A digital-to-analog converter, including an input to receive a digital signal; a first comparator configured to receive the digital signal and output a first signal based on the digital signal and a first threshold; a second comparator configured to receive the digital signal and output a second signal based on the digital signal and a second threshold, the second threshold different from the first threshold; and an integrator configured to receive the first signal and the second signal and integrate the first signal and the second signal into an analog signal that represents the digital signal.

An interface circuit to an electromagnetic flow sensor is described. In an example, it can provide a DC coupled signal path from the electromagnetic flow sensor to an analog-to-digital converter (ADC) circuit. Examples with differential and pseudo-differential signal paths are described. Examples providing DC offset or low frequency noise compensation or cancellation are described. High input impedance examples are described. Coil excitation circuits are described, such as can provide on-chip inductive isolation between signal inputs and signal outputs. A switched mode power supply can be used to actively manage a bias voltage of an H-Bridge, such as to boost the current provided by the H-Bridge to the sensor coil during select time periods, such as during phase shift time periods of the coil, which can help reduce or minimize transient noise during such time periods.

An interface circuit to an electromagnetic flow sensor is described. In an example, it can provide a DC coupled signal path from the electromagnetic flow sensor to an analog-to-digital converter (ADC) circuit. Examples with differential and pseudo-differential signal paths are described. Examples providing DC offset or low frequency noise compensation or cancellation are described. High input impedance examples are described. Coil excitation circuits are described, such as can provide on-chip inductive isolation between signal inputs and signal outputs. A switched mode power supply can be used to actively manage a bias voltage of an H-Bridge, such as to boost the current provided by the H-Bridge to the sensor coil during select time periods, such as during phase shift time periods of the coil, which can help reduce or minimize transient noise during such time periods.

Apparatus and associated methods relate to modulating polarity on sample outputs from a time-interleaved analog-to-digital converter (TIADC) as an input to a time skew extractor in a clock skew calibration control loop. In an illustrative example, a multiplier-mixer may impart a polarity change to every other data sample transmitted between the TIADC and the time skew extractor. In some examples, a multiplexer may select between the polarity modulated samples and non-polarity modulated samples before the multiplier-mixer. Selection between the polarity modulated samples and the non-polarity modulated samples may be based on, for example, determination of specific frequency bands of an analog input signal. Various embodiments may improve convergence of clock skew calibration control loops for analog input signals sampled with a TIADC near a Nyquist frequency.

A PDM (pulse density modulation) signal energy detection circuit includes a digital-to-analog converter circuit for receiving a PDM digital input signal and producing an analog output signal based on the PDM digital input signal. The PDM signal energy detection circuit also includes a comparator circuit for receiving the analog output signal from the digital-to-analog converter circuit and producing a pulsed signal when a magnitude of the analog output signal exceeds a pre-set threshold. The PDM signal energy detection circuit also has a counter circuit for receiving the pulsed signal from the comparator circuit and producing an energy detection signal when a number of consecutive pulsed signals exceed a pre-set count.