Technologies for low jitter and low power ring oscillators with multi-phase signal reassembly are described. A ring oscillator circuit includes a ring oscillator with a set of M delay stages, each stage outputs a phase signal, where M is a positive integer greater than one. The ring oscillator circuit includes a phase selector circuit coupled to the ring oscillator. The phase selector circuit can receive M phase signals from the ring oscillator and generate N phase signals based on the M phase signals, where N is a positive integer less than M.

Alignment circuitry including a first clocked latch for receiving a synchronization signal having an enable edge and a target clock signal and outputting an enable signal having an enable edge corresponding to the enable edge of the synchronization signal and synchronized with the target clock signal; a second clocked latch for receiving the enable signal and a delayed target clock signal, being a version of the target clock signal having been delayed by a delay circuit of the clock-controlled circuitry, and outputting a re-timed enable signal having an enable edge corresponding to the enable edge of the enable signal and synchronized with the delayed target clock signal; and gating circuitry for receiving the delayed target clock signal and the re-timed enable signal and to start output of the delayed target clock signal at a timing defined by the enable edge of the re-timed enable signal for controlling the clock-controlled circuitry.

Alignment circuitry including a first clocked latch for receiving a synchronization signal having an enable edge and a target clock signal and outputting an enable signal having an enable edge corresponding to the enable edge of the synchronization signal and synchronized with the target clock signal; a second clocked latch for receiving the enable signal and a delayed target clock signal, being a version of the target clock signal having been delayed by a delay circuit of the clock-controlled circuitry, and outputting a re-timed enable signal having an enable edge corresponding to the enable edge of the enable signal and synchronized with the delayed target clock signal; and gating circuitry for receiving the delayed target clock signal and the re-timed enable signal and to start output of the delayed target clock signal at a timing defined by the enable edge of the re-timed enable signal for controlling the clock-controlled circuitry.

Analog-to-digital converters (ADCs) of an integrated circuit includes a first set of ADCs and second set of ADCs in which the ADCs of the first set are of a different type than the ADCs of the second set. On-chip testing of the ADCs includes calibrating an N-bit differential digital-to-analog converter (DAC) and storing a pair of calibration codes for each of 2.sup.N possible DAC input codes for the DAC in an on-chip memory. The first set of ADCs is tested using the pairs of calibration codes stored in the on-chip memory and a full N-bit resolution of the DAC. Subsequently, the second set of ADCs is tested using pairs of calibration codes corresponding to a reduced M-bit resolution of the DAC, in which M is less than N. During the testing of the second set of ADCs, a portion of the calibration codes stored in the on-chip memory is overwritten.

The invention relates to a method for determining the phase difference between a first clock signal (CK1) received by a first electronic component (CE1) and a second clock signal (CK2) received by a second electronic component (CE2), comprising the steps of: S10) transmitting a first calibration signal (S12); S20) measuring a first delay (T.sub.1); S30) transmitting a second calibration signal (S21); S40) measuring a second delay (T.sub.2); S50) measuring the number (n) of clock pulses between the transmission of the first calibration signal (S12) and the active edge of the first clock signal (CK1) consecutive to the active edge of the second calibration signal (S21); S60) determining the phase difference depending on the parity of the number (n) of clock pulses.

A method of an optical sensor device includes: providing an optical sensor for receiving reflected light associated with a light emission unit to generate at least one sensed image; using a first exposure setting to make the optical sensor generate a first frame data during a first frame time period of a frame; when performing an exposure adjustment operation, using a second exposure setting to make the optical sensor generate a second frame data during a second time period of the frame neighbor to the first frame time period of the frame; and, generating a normalized digital signal corresponding to the first frame data based on the relation between the first frame data and the second frame data.

A method of an optical sensor device includes: providing an optical sensor for receiving reflected light associated with a light emission unit to generate at least one sensed image; using a first exposure setting to make the optical sensor generate a first frame data during a first frame time period of a frame; when performing an exposure adjustment operation, using a second exposure setting to make the optical sensor generate a second frame data during a second time period of the frame neighbor to the first frame time period of the frame; and, generating a normalized digital signal corresponding to the first frame data based on the relation between the first frame data and the second frame data.

A segmented resistor string type digital to analog converter comprises: a most significant bit (MSB) resistor string (104) comprising a high level resistor string, an intermediate level resistor string and a ground level resistor string; a decoding circuit (101), configured to decode an n-bit code of the MSB resistor string (104) and output 2.sup.n decoded codes; a logic sequential generation circuit (102), connected to the decoding circuit (101) and configured to perform a logic operation on a middle-position code among the 2.sup.n decoded codes and a refresh clock signal in non-overlapping sequences, and output two groups of control signals with completely complementary high level durations; a control signal bootstrap circuit (103), connected to the logic sequential generation circuit (102) and configured to perform bootstrap processing on the control signal, and increase the high level of the control signal to a sum of a power supply voltage and a threshold voltage; and a first switch group (106), connected to the control signal bootstrap circuit (103) and the intermediate level resistor string, where on/off of the first switch group (106) is controlled by the control signal after the bootstrap processing, so as to connect the intermediate level resistor string to the circuit or disconnect the intermediate level resistor string from the circuit.

A method includes receiving samples of digital to analog converter (DAC), partitioning the samples to unit-DACs based upon previous partitions of inputs to the unit-DACs to cancel out integrated non-linearities of outputs of the DAC caused by the gain mismatches of the unit-DACs, including partitioning samples of DAC input to the unit-DACs through a recursive nth order partitioning algorithm. The algorithm includes, for each DAC input, determining a first partition of the DAC input that would cancel an (n1)th order previously integrated non-linearity, adding an equivalent DAC input of the first partition to the DAC input to obtain a total DAC input, using a first order application of the total DAC input to the inputs of the unit-DACs to yield a second partition of DAC input, summing the first and second partitions generate a final partition, and, based on the final partition, computing non-linearity remainders at each order of integration.

A variable resistor may be coupled between a reference voltage source and components of an integrated circuit to reduce issues relating to thermal noise from a reference voltage signal generated by the reference voltage source. The variable resistor may be set to a low level during a first time period and a high level during a second time period, in which the time periods correspond to a sampling period of a switched-capacitor circuit. The low resistance time period may allow quick settling of an input reference voltage signal, whereas the high resistance time period may reduce a bandwidth of noise on a sampling capacitor coupled to the reference voltage signal. The variable resistor and switched-capacitor network may be used in an analog-to-digital converter (ADC), such as in audio circuits.