Methods and systems for electro-absorption modulator drivers in CMOS may comprise an electro-absorption modulator optically coupled to a laser source and electrically coupled to a modulator driver circuit that is in a complementary metal oxide semiconductor (CMOS) chip. The electro-absorption modulator includes a summer for receiving a negative bias voltage and a programmable offset voltage, a voltage regulator for receiving the output of the summer and generating a negative DC voltage of lower magnitude than the negative bias voltage, level shifting circuitry for shifting a received data signal to a DC voltage level between the negative DC voltage from the voltage regulator and the negative bias voltage, and an electrical coupling structure for DC-coupling the level shifted data signal to the modulator. The bias voltage may be received from an off-chip low drop out (LDO) voltage regulator. The level shifting circuitry may include cascode CMOS transistors and a current mirror.

Certain aspects of the present disclosure provide a digital-to-analog converter (DAC). The DAC generally includes a plurality of transistors selectively coupled to an output of the DAC, and a biasing circuit coupled to gates of the plurality of transistors. The biasing circuit may include a first transistor having a gate coupled to a drain of the first transistor, a first buffer having an input coupled to the gate of the first transistor, a second transistor having a gate coupled to an output of the first buffer, a first resistive-capacitive (RC) circuit having a first resistive element and a first capacitive element, the first RC circuit being coupled between the gate of the first transistor and the gate of the second transistor, and a first switch coupled between the first resistive element and the first capacitive element.

A second-order modulator includes a plurality of integrators and a parallel higher-bit processing part, and the parallel higher-bit processing part includes a plurality of addition and determination processing sections. The addition and determination processing section receives first and second carry inputs and first and second state inputs, and outputs a quantized output and first and second state outputs. A first selector selects one set from sets of the first and the second state outputs from the plurality of addition and determination processing sections and outputs the selected set, and a second selector selects one quantized output from the quantized outputs from the plurality of addition and determination processing sections. An output of the first selector is used as a selection control signal for the first and the second selectors.

A second-order modulator includes a plurality of integrators and a parallel higher-bit processing part, and the parallel higher-bit processing part includes a plurality of addition and determination processing sections. The addition and determination processing section receives first and second carry inputs and first and second state inputs, and outputs a quantized output and first and second state outputs. A first selector selects one set from sets of the first and the second state outputs from the plurality of addition and determination processing sections and outputs the selected set, and a second selector selects one quantized output from the quantized outputs from the plurality of addition and determination processing sections. An output of the first selector is used as a selection control signal for the first and the second selectors.

In method for processing a measured-value signal determined in an analog manner and a resolver system for implementing the method, the measured-value signal being supplied to a delta-sigma modulator, which makes a bit stream, particularly a one-bit data stream, available on the output side, in particular, whose moving average corresponds to the measured-value signal, the bit stream being supplied to a first digital filter, which converts the bit stream into a stream of digital intermediate words, that is a multibit data stream, the first digital filter having three serially arranged differentiators, the bit stream being clocked at a clock frequency f.sub.S, that is, at a clock-pulse period T.sub.S=1/f.sub.S, and therefore the stream of digital intermediate words being clocked, and thus updated, at a clock-pulse frequency f.sub.D, that is, at a clock-pulse period T.sub.D=1/f.sub.D, the output signal of the first digital filter being supplied to a second digital filter, the second digital filter having as its output data-word stream the difference between a first and a second result data-word stream, the first and second result data-word stream being determined around a first and second time interval from the intermediate data-word stream, the first and second time interval being situated at a distance in time T1, the first result data-word stream being determined as a time-discrete second derivation with time scale TD and the second result data-word stream being determined as a time-discrete second derivation with time scale TD.

In method for processing a measured-value signal determined in an analog manner and a resolver system for implementing the method, the measured-value signal being supplied to a delta-sigma modulator, which makes a bit stream, particularly a one-bit data stream, available on the output side, in particular, whose moving average corresponds to the measured-value signal, the bit stream being supplied to a first digital filter, which converts the bit stream into a stream of digital intermediate words, that is a multibit data stream, the first digital filter having three serially arranged differentiators, the bit stream being clocked at a clock frequency f.sub.S, that is, at a clock-pulse period T.sub.S=1/f.sub.S, and therefore the stream of digital intermediate words being clocked, and thus updated, at a clock-pulse frequency f.sub.D, that is, at a clock-pulse period T.sub.D=1/f.sub.D, the output signal of the first digital filter being supplied to a second digital filter, the second digital filter having as its output data-word stream the difference between a first and a second result data-word stream, the first and second result data-word stream being determined around a first and second time interval from the intermediate data-word stream, the first and second time interval being situated at a distance in time T1, the first result data-word stream being determined as a time-discrete second derivation with time scale TD and the second result data-word stream being determined as a time-discrete second derivation with time scale TD.

A source driver and an operation method thereof are provided. The source driver includes an output buffer, a feedback switch, and a feedback voltage generating circuit. The output buffer receives the input voltage and produces an output voltage. The first terminal and the second terminal of the feedback switch are respectively coupled to the input terminal and the output terminal of the output buffer. During an overdrive period, the feedback switch is turned off, and the feedback voltage generating circuit outputs a feedback voltage to the output buffer. The feedback voltage is lower than the output voltage when the input voltage is in a rising mode. The feedback voltage is higher than the output voltage when the input voltage is in a falling mode. During a normal driving period, the feedback switch is turned on, and the feedback voltage generating circuit does not output the feedback voltage.

A source driver and an operation method thereof are provided. The source driver includes an output buffer, a feedback switch, and a feedback voltage generating circuit. The output buffer receives the input voltage and produces an output voltage. The first terminal and the second terminal of the feedback switch are respectively coupled to the input terminal and the output terminal of the output buffer. During an overdrive period, the feedback switch is turned off, and the feedback voltage generating circuit outputs a feedback voltage to the output buffer. The feedback voltage is lower than the output voltage when the input voltage is in a rising mode. The feedback voltage is higher than the output voltage when the input voltage is in a falling mode. During a normal driving period, the feedback switch is turned on, and the feedback voltage generating circuit does not output the feedback voltage.

A wired communication apparatus includes a receiver, a transmitter and a control circuit. The receiver includes a signal detection circuit. The transmitter includes a number of digital-to-analog converter (DAC) cells. The control circuit can receive an overvoltage signal from the receiver and can disable an output of the transmitter based on the overvoltage signal. The signal detection circuit is operable in a special mode to detect an overvoltage event at an input port of the receiver, and the control circuit can disable the output of the transmitter for a programmable time period.

A wired communication apparatus includes a receiver, a transmitter and a control circuit. The receiver includes a signal detection circuit. The transmitter includes a number of digital-to-analog converter (DAC) cells. The control circuit can receive an overvoltage signal from the receiver and can disable an output of the transmitter based on the overvoltage signal. The signal detection circuit is operable in a special mode to detect an overvoltage event at an input port of the receiver, and the control circuit can disable the output of the transmitter for a programmable time period.