According to examples, an apparatus may include an arithmetic logic unit (ALU) to apply a modification function to a digital input signal to generate a modified digital input signal, a digital-to-analog converter (DAC) to convert the modified digital input signal to an analog input signal, a crossbar array to apply an operation on the analog input signal to generate an analog output signal, and an analog-to-digital converter (ADC). The ADC may modify the analog output signal to compensate for application of the modification function to the digital input signal, may convert the modified analog output signal to a digital output signal, and may output the digital output signal.

A coarse tuning synthesizer for wireless communication includes a digital control unit, a digital-to-analog converter, and a comparator. The digital control unit includes an output node coupled to a first input node of a VCO (voltage controlled oscillator). The digital-to-analog converter includes a first node coupled to the first input node of the VCO. The comparator includes an output node coupled to an input node of the digital control unit. The comparator also includes a first input node coupled to a second node of the digital-to-analog converter and a second input node coupled to an output node of the VCO.

A coarse tuning synthesizer for wireless communication includes a digital control unit, a digital-to-analog converter, and a comparator. The digital control unit includes an output node coupled to a first input node of a VCO (voltage controlled oscillator). The digital-to-analog converter includes a first node coupled to the first input node of the VCO. The comparator includes an output node coupled to an input node of the digital control unit. The comparator also includes a first input node coupled to a second node of the digital-to-analog converter and a second input node coupled to an output node of the VCO.

An apparatus is provided which comprises: a frequency locked loop (FLL) comprising an oscillator including a plurality of delay stages, wherein an output of each delay stage is counted to determine a frequency of the FLL; and one or more circuitries coupled to the FLL to adjust a power supply to the FLL according to the determined frequency of the FLL.

An apparatus is provided which comprises: a frequency locked loop (FLL) comprising an oscillator including a plurality of delay stages, wherein an output of each delay stage is counted to determine a frequency of the FLL; and one or more circuitries coupled to the FLL to adjust a power supply to the FLL according to the determined frequency of the FLL.

A method in a transmitter circuit of generating a signal comprising a first sequence of OFDM symbols, which are to be transmitted within a frequency sub band of a second sequence of OFDM symbols is disclosed. A first cyclic prefix (CP) of the second sequence of OFDM symbols has a first duration, and a second CP of the second sequence of OFDM symbols has a second duration. In order to generate both the first and the second cyclic prefix with an integer number of equidistant samples, a first sampling rate is required. The method comprises generating the signal comprising the first sequence of OFDM symbols at a second sampling rate, lower than the first sampling rate, and adjusting a sampling phase during CPs.

An ADC and an analog-to-digital conversion method are provided. The ADC includes: a clock generator, including M transmission gates, where the M transmission gates are configured to receive a first clock signal that is periodically sent and separately perform gating control on the first clock signal, so as to generate M second clock signals, M is an integer that is greater than or equal to 2; M ADC channels that are configured in a time interleaving manner, configured to receive one analog signal and separately perform, under the control of the M second clock signals, sampling and analog-to-digital conversion on the analog signal, so as to obtain M digital signals, where each ADC channel is corresponding to one clock signal of the M second clock signals; and an adder, configured to add the M digital signals together in a digital field, so as to obtain a digital output signal.

A digital-to-analog converter including a resistor string configured to provide a plurality of gradation voltages formed by receiving a top voltage at one end thereof and a bottom voltage at the other end; a plurality of pass transistors including a pass transistor having one end which is electrically connected to the resistor string and outputting any one among the plurality of gradation voltages; and a decoder configured to control the plurality of pass transistors. The plurality of the pass transistors are included in any one among a plurality of groups according to values of the gradation voltages, and the pass transistors included in the any one group are divided into a first group and a second group according to output gradation voltages, and pass transistors included in the first group and pass transistors included in the second group are different types of pass transistors.

A digital-to-analog converter including a resistor string configured to provide a plurality of gradation voltages formed by receiving a top voltage at one end thereof and a bottom voltage at the other end; a plurality of pass transistors including a pass transistor having one end which is electrically connected to the resistor string and outputting any one among the plurality of gradation voltages; and a decoder configured to control the plurality of pass transistors. The plurality of the pass transistors are included in any one among a plurality of groups according to values of the gradation voltages, and the pass transistors included in the any one group are divided into a first group and a second group according to output gradation voltages, and pass transistors included in the first group and pass transistors included in the second group are different types of pass transistors.

The disclosure relates to a phase shifter having a first mode of operation and a second mode of operation, the phase shifter comprising a mixer stage configured to mix an oscillator signal with an analog signal to provide a phase shifted signal, switching circuitry and a controller arranged to provide the analog signal to the mixer stage as a voltage in the first mode of operation and as a current in the second mode of operation.