The disclosure relates to a phase shifter having a first mode of operation and a second mode of operation, the phase shifter comprising a mixer stage configured to mix an oscillator signal with an analog signal to provide a phase shifted signal, switching circuitry and a controller arranged to provide the analog signal to the mixer stage as a voltage in the first mode of operation and as a current in the second mode of operation.

A list of digital elements to be sorted are converted to a group of analog signals. The group of analog signals are simultaneously compared to each other to determine the largest analog signal in the group. The largest analog signal is then compared to each of the analog signals in the group to determine which one or more of the analog signals in the group matches the largest analog signal. The matching one or more of the analog signals is removed from the group and the process is repeated until the group of analog signals have been sorted.

A list of digital elements to be sorted are converted to a group of analog signals. The group of analog signals are simultaneously compared to each other to determine the largest analog signal in the group. The largest analog signal is then compared to each of the analog signals in the group to determine which one or more of the analog signals in the group matches the largest analog signal. The matching one or more of the analog signals is removed from the group and the process is repeated until the group of analog signals have been sorted.

A device has a digital-to-analog converter to convert waveform data into analog waveforms, a waveform memory to store stored waveform data, an external waveform interface to receive real-time waveform data from an external device, a waveform multiplexer connected to the digital-to-analog converter to select between the first memory and the external waveform interface, a sequencer to receive and execute instructions to identify and access waveform data to drive the digital-to-analog converter, a sequencer instruction memory to provide stored instructions to the sequencer, an external instruction interface to receive real-time instructions for the sequencer, and a sequencer multiplexer to select between the sequencer instruction memory and the external instruction interface connected to the sequencer. A method of controlling a waveform generator includes selecting a mode of operation, where the mode of operation is selected from streaming waveform data, real-time waveform memory updates, real-time sequencer instructions, real-time sequencer instruction updates, and real-time sequencer flow control.

A gamma correction digital-to-analog converter (DAC) includes a first DAC circuit, a second DAC circuit and a voltage generator. The first DAC circuit includes a plurality of first transistors and is configured to receive a plurality of first reference gamma voltages and 1 upper bits of k-bit digital data and generate a first gamma voltage based on the 1 upper bits of the k-bit digital data and the first reference gamma voltages. The second DAC circuit includes a plurality of second transistors and is configured to receive a plurality of second reference gamma voltages and m lower bits of the k-bit digital data and generate a second gamma voltage based on the m lower bits of the k-bit digital data and the second reference gamma voltages. The voltage generator is configured to generate a bulk voltage and supply the generated bulk voltage to a bulk terminal of each of the first transistors or supply the generated bulk voltage to a bulk terminal of each of the second transistors to generate a gamma correction analog signal according to the first gamma voltage and the second gamma voltage. A data driver including a gamma correction DAC and a method thereof are also introduced.

A gamma correction digital-to-analog converter (DAC) includes a first DAC circuit, a second DAC circuit and a voltage generator. The first DAC circuit includes a plurality of first transistors and is configured to receive a plurality of first reference gamma voltages and 1 upper bits of k-bit digital data and generate a first gamma voltage based on the 1 upper bits of the k-bit digital data and the first reference gamma voltages. The second DAC circuit includes a plurality of second transistors and is configured to receive a plurality of second reference gamma voltages and m lower bits of the k-bit digital data and generate a second gamma voltage based on the m lower bits of the k-bit digital data and the second reference gamma voltages. The voltage generator is configured to generate a bulk voltage and supply the generated bulk voltage to a bulk terminal of each of the first transistors or supply the generated bulk voltage to a bulk terminal of each of the second transistors to generate a gamma correction analog signal according to the first gamma voltage and the second gamma voltage. A data driver including a gamma correction DAC and a method thereof are also introduced.

An example timing error measurement system includes a digital-to-analog converter (DAC) having a plurality of current steering circuits, the DAC responsive to a clock signal, a one-bit comparator coupled to a differential output of the DAC, a filter coupled to an output of the one-bit comparator, control logic coupled to an output of the filter, and a delay line coupled to an output of the control logic. An output of the delay line is coupled to an input of the one-bit comparator. The delay line is configured to delay the clock signal.

An example timing error measurement system includes a digital-to-analog converter (DAC) having a plurality of current steering circuits, the DAC responsive to a clock signal, a one-bit comparator coupled to a differential output of the DAC, a filter coupled to an output of the one-bit comparator, control logic coupled to an output of the filter, and a delay line coupled to an output of the control logic. An output of the delay line is coupled to an input of the one-bit comparator. The delay line is configured to delay the clock signal.

A integrated circuit device includes digital-to-analog converter (DAC) circuitry including a resistor DAC that includes a resistor-two-resistor DAC configured to receive a first sub-word that includes a most significant bit (MSB) of a digital input signal and to output an analog output signal representative of the first sub-word, a resistor ladder configured to receive the analog output signal and a second sub-word that includes an intermediate significant bit (ISB) of the digital input signal and to generate an analog interpolated signal. The resistor ladder includes a plurality of resistor elements connected in series with one another to define a plurality of tap nodes, wherein a respective tap node is arranged between every two adjacent ones of the resistor elements, and a switching circuit having plurality of switches, wherein each switch is configured to selectively connect a respective one of the tap nodes to an output of the resistor ladder to generate the analog interpolated signal.

The present disclosure discloses a digital-to-analog converter (DAC) design which is suitable for providing a high output power high-speed DAC, e.g., in radio frequency applications. The DAC design utilizes a parallel DAC structure, e.g., having 8 parallel DACs and an aggregate current output, to provide a high and programmable current output (in some implementations, up to 512 mA or more). The parallel DAC structure alleviates the design problems which exist in trying to output a high amount of current using a single DAC. The DAC design further utilizes a hybrid structure which integrates the signal chain for a more reliable system. In some embodiments, the hybrid structure uses a CMOS process for the current sources and switches and a GaAs cascode stage for combining the outputs to optimally leverage the advantages of both technologies. The result is a highly efficient DAC (with peak output power programmable up to 29 dBm or more).