Clock alignment circuitry may include phase detection circuitry and programmable delay circuitry to facilitate aligning a data signal with a particular state of a clock signal. For example, phase detection circuitry may be disposed at a location of interest to monitor the relative timing of the clock signal and the data signal. Based on the monitored states, the programmable delay circuitry may determine the delay to be applied to the data signal (e.g., prior to propagating through logic operations and transmission to the location of interest) such that the data signal later arrives at the location of interest at a suitable time. Effectively, a programmable delay is added to the delay encountered by the data signal during processing and transmission to the location of interest such that the total delay results in the data signal arriving at the location of interest while the clock signal is in the desired state.

A signal generation circuit including a first control circuit, a second control circuit, an arbiter circuit, and a digital-to-analog converter (DAC) circuit is provided. The first control circuit stores a first string of data. The first control circuit enables a first trigger signal in response to a first event occurring. The second control circuit stores a second string of data. The second control circuit enables a second trigger signal in response to a second event occurring. The arbiter circuit reads the first or second control circuit according to the order of priority to use the first string of data or the second string of data as a digital input in response to the first and second trigger signals being enabled. The DAC circuit converts the digital input to generate an analog output.

A neurostimulator incorporating a novel chip design that uses the principle of redundant signal crossfiring to overcome electronic component mismatch error in general and transistor mismatch error in particular, to yield superior quality neurostimulation signal generation, useful in enhancing the bidirectional human-machine interface in prosthesis operation for the restoration of somatosensation for an amputee; and an improvement thereof additionally comprising a digital-to-analog converter device, that includes a number of unit cells, each unit cell being associated with a unit cell size indicating manufacturing specifications of the unit cell, and that further includes a plurality of switches, each being coupled to a component, and an output electrode coupled to the plurality of switches, and wherein the digital-to-analog converter device is configured to output an output signal at the output electrode.

A method of calibrating a radio frequency (RF) circuit that includes an in-phase path (I-path) and a quadrature-phase path (Q-path) is provided. The I-path includes a first modulator and a first component, and the Q-path includes a second modulator and a second component. The modulators and the components respectively include a current DAC (IDAC). The calibration method includes: calibrating DC offsets of the first and second modulators to obtain a first setting value; swapping the I-path and the Q-path, and calibrating DC offsets of the first and second modulators again to obtain a second setting value; setting the IDACs of the first and second modulators with a value of a function of the first and second setting values; calibrating DC offsets of the first and second components; calibrating DC offsets of the first and second modulators; and calibrating DC offsets of the first and second components.

A method of calibrating a radio frequency (RF) circuit that includes an in-phase path (I-path) and a quadrature-phase path (Q-path) is provided. The I-path includes a first modulator and a first component, and the Q-path includes a second modulator and a second component. The modulators and the components respectively include a current DAC (IDAC). The calibration method includes: calibrating DC offsets of the first and second modulators to obtain a first setting value; swapping the I-path and the Q-path, and calibrating DC offsets of the first and second modulators again to obtain a second setting value; setting the IDACs of the first and second modulators with a value of a function of the first and second setting values; calibrating DC offsets of the first and second components; calibrating DC offsets of the first and second modulators; and calibrating DC offsets of the first and second components.

In described examples, a circuit includes an integrator. The integrator generates a first signal responsive to an input signal. A trigger circuit is coupled to the integrator and receives the first signal. A charge dump circuit is coupled to the integrator and the trigger circuit. The trigger circuit modifies configuration of the charge dump circuit and the integrator when the first signal is greater than a first threshold.

A thermodynamic housing for a geophysical data acquisition system is provided. The housing includes a novel enclosure cooling system with strategically placed ducting and insulation which maintains proper controller temperature and elevated temperature ambient environments. A novel node enclosure is provided which includes a fail safe 4 bar linkage toggle to ground stakes which enhances physical stability and electrical connectivity.

An isolation amplifier of an embodiment includes: a primary circuit including an encoder configured to encode an input signal and output the encoded input signal and an anomaly detection circuit configured to detect anomaly having occurred to the input signal and generate a detection signal; an isolation unit configured to insulate the primary circuit from a secondary circuit; an output circuit configured to generate an output signal corresponding to the input signal; and an anomaly-input sensing-output circuit configured to generate an output signal from the secondary circuit by changing the output signal from the output circuit based on the detection signal.

A receiver is described, the receiver comprising an ABB filter stage, an ADC stage. The ABB filter stage comprises an ABB filter stage input configured to receive an analog baseband, BB, signal and an ABB filter stage output configured to provide a filtered analog BB signal. The ADC stage comprises an ADC stage input configured to receive the filtered analog BB signal and an ADC stage output configured to provide a digital BB signal. The ADC stage comprises an ADC comprising an ADC input configured to receive the filtered analog BB signal or a signal derived therefrom as an ADC input signal, and wherein the ADC is configured to perform an analog-to-digital, A/D, conversion of the ADC input signal to derive the digital BB signal.

A receiver is described, the receiver comprising an ABB filter stage, an ADC stage. The ABB filter stage comprises an ABB filter stage input configured to receive an analog baseband, BB, signal and an ABB filter stage output configured to provide a filtered analog BB signal. The ADC stage comprises an ADC stage input configured to receive the filtered analog BB signal and an ADC stage output configured to provide a digital BB signal. The ADC stage comprises an ADC comprising an ADC input configured to receive the filtered analog BB signal or a signal derived therefrom as an ADC input signal, and wherein the ADC is configured to perform an analog-to-digital, A/D, conversion of the ADC input signal to derive the digital BB signal.