The present application provides a capacitance sensing circuit, comprising an integrating circuit, comprising an integrating input terminal, coupled to the touch capacitance, wherein the integrating input terminal receives an input voltage; and an integrating output terminal, configured to output an output voltage; a comparator; a positive digital-to-analog (DA) converting unit; a negative DA converting unit; a control circuit, configured to control the positive DA converting unit and the negative DA converting unit; and a logic circuit, configured to output an output code, wherein the output code is related to a capacitance of the touch capacitance.

The present application provides a capacitance sensing circuit, comprising an integrating circuit, comprising an integrating input terminal, coupled to the touch capacitance, wherein the integrating input terminal receives an input voltage; and an integrating output terminal, configured to output an output voltage; a comparator; a positive digital-to-analog (DA) converting unit; a negative DA converting unit; a control circuit, configured to control the positive DA converting unit and the negative DA converting unit; and a logic circuit, configured to output an output code, wherein the output code is related to a capacitance of the touch capacitance.

Disclosed is a calibration circuit and method. The circuit includes: a DAC that outputs an analog parameter and includes output parameter adjustment circuitry; a comparator that receives a reference parameter and the analog parameter; and a control circuit (with select logic) connected to the comparator and DAC in a feedback loop. During a calibration mode, the magnitude of the analog parameter is adjusted by DAC step in one direction and the feedback loop is used to perform a binary search calibration process. During an operation mode, the magnitude of the analog parameter is adjusted by DAC step in the opposite direction. The select logic selects the DAC step identified by the calibration process or the next higher DAC step as a final DAC step. The control circuit outputs a final DAC code corresponding to the final DAC step and the DAC generates a calibrated parameter based thereon.

Disclosed is a calibration circuit and method. The circuit includes: a DAC that outputs an analog parameter and includes output parameter adjustment circuitry; a comparator that receives a reference parameter and the analog parameter; and a control circuit (with select logic) connected to the comparator and DAC in a feedback loop. During a calibration mode, the magnitude of the analog parameter is adjusted by DAC step in one direction and the feedback loop is used to perform a binary search calibration process. During an operation mode, the magnitude of the analog parameter is adjusted by DAC step in the opposite direction. The select logic selects the DAC step identified by the calibration process or the next higher DAC step as a final DAC step. The control circuit outputs a final DAC code corresponding to the final DAC step and the DAC generates a calibrated parameter based thereon.

The present disclosure provides a digital to analog conversion (DAC) circuit and a data source circuit chip, the DAC circuit includes: first MOS tubes with the same number of the inputted digital bits; a second resistance, one end of the second resistance connects to the reference voltage, another end of the second resistance connects to the output terminal of the circuit; a second MOS tube, the drain of the second MOS tube connects to the output terminal of the circuit, the gate of the second MOS tube receives a row blank signal; and a capacitor, one end of the capacitor connects to the output terminal, another end of the capacitor is grounded. Using the above circuit and data source circuit chip, can greatly reduce the number of the MOS tube used in the DAC circuit, to effectively reduce the volume of the data source circuit chip and cost.

The present disclosure provides a digital to analog conversion (DAC) circuit and a data source circuit chip, the DAC circuit includes: first MOS tubes with the same number of the inputted digital bits; a second resistance, one end of the second resistance connects to the reference voltage, another end of the second resistance connects to the output terminal of the circuit; a second MOS tube, the drain of the second MOS tube connects to the output terminal of the circuit, the gate of the second MOS tube receives a row blank signal; and a capacitor, one end of the capacitor connects to the output terminal, another end of the capacitor is grounded. Using the above circuit and data source circuit chip, can greatly reduce the number of the MOS tube used in the DAC circuit, to effectively reduce the volume of the data source circuit chip and cost.

Embodiments of the present invention disclose a power line communications device, and the power line communications device includes a USB interface, a protocol conversion module, a signal conversion module, a coupler, and a power line interface. A first end of the USB interface is connected to a first end of the protocol conversion module, a second end of the protocol conversion module is connected to a first end of the signal conversion module, a second end of the signal conversion module is connected to a first end of the coupler, and a second end of the coupler is connected to a first end of the power line interface. During implementation of the embodiments of the present invention, the USB interface may be used to provide a network signal for a terminal device.

Embodiments of the present invention disclose a power line communications device, and the power line communications device includes a USB interface, a protocol conversion module, a signal conversion module, a coupler, and a power line interface. A first end of the USB interface is connected to a first end of the protocol conversion module, a second end of the protocol conversion module is connected to a first end of the signal conversion module, a second end of the signal conversion module is connected to a first end of the coupler, and a second end of the coupler is connected to a first end of the power line interface. During implementation of the embodiments of the present invention, the USB interface may be used to provide a network signal for a terminal device.

The present invention discloses a capacitor layout of a digital-to-analog conversion integrated circuit (DAC IC), comprising a first capacitor group, a second capacitor group and a third capacitor group. The first capacitor group, located within an interior layout area of the capacitor layout, determines a most significant bit (MSB) of the DAC IC and includes a plurality of capacitor units coupled between a first upper circuit and a first lower circuit. The second capacitor group, located within the interior layout area, determines a non-MSB bit of the DAC IC and includes at least one capacitor unit(s) coupled between a second upper circuit and a second lower circuit. The third capacitor group includes a plurality of capacitor units coupled between a third upper circuit and a third lower circuit which are not short-circuited; the capacitor units of the third capacitor group are disposed around the interior layout area.

Provided, among other things, is an apparatus that converts a signal from one sampling domain to another, and which includes: an input line for accepting an input signal and a processing branch. The processing branch includes a branch input coupled to the input line for inputting data samples that are discrete in time and in value, a quadrature downconverter, a first and second lowpass filter, a first and second polynomial interpolator, and a rotation matrix multiplier that provides a phase rotation. The processing branch generates data samples at a sampling interval that differs from the sampling interval associated with the signal provided to the branch input, e.g., with the difference in the sampling intervals depending on fluctuations in the output period of a local oscillator. Certain embodiments include multiple such processing branches, e.g., operating on different frequency bands of the input signal.