A voltage regulator has a comparator and a reference voltage coupled to a first input of the comparator. An output voltage of the voltage regulator is coupled to a second input of the comparator through a resistor. A current source is coupled to the second input of the comparator. The first current source can be a first digital-to-analog converter (DAC). A second current source can be coupled in parallel with the first DAC. The second current source can be a second DAC. The voltage regulator can include a boost topology.

A voltage regulator has a comparator and a reference voltage coupled to a first input of the comparator. An output voltage of the voltage regulator is coupled to a second input of the comparator through a resistor. A current source is coupled to the second input of the comparator. The first current source can be a first digital-to-analog converter (DAC). A second current source can be coupled in parallel with the first DAC. The second current source can be a second DAC. The voltage regulator can include a boost topology.

A mixed signal system includes a digital domain and an analog domain. The analog domain includes a plurality of BARs. Each BAR includes addressable registers. The digital domain includes an interface configured to communicate with the analog domain, e.g., write data to an addressable register within a BAR by transmitting a first select signal to select a first BAR of the plurality of BARs. The interface transmits an address of the addressable register of the first BAR and broadcasts the write data to the first BAR and at least one BAR other than the first BAR. The analog domain transmits data from a second BAR of the plurality of BARs to the digital domain by gating a select BAR signal associated with each BAR with its corresponding content stored therein to form respective BAR output and further by gating the respective BAR outputs with one another.

A mixed signal system includes a digital domain and an analog domain. The analog domain includes a plurality of BARs. Each BAR includes addressable registers. The digital domain includes an interface configured to communicate with the analog domain, e.g., write data to an addressable register within a BAR by transmitting a first select signal to select a first BAR of the plurality of BARs. The interface transmits an address of the addressable register of the first BAR and broadcasts the write data to the first BAR and at least one BAR other than the first BAR. The analog domain transmits data from a second BAR of the plurality of BARs to the digital domain by gating a select BAR signal associated with each BAR with its corresponding content stored therein to form respective BAR output and further by gating the respective BAR outputs with one another.

A novel and useful variable step serial DAC having a desired trajectory between input samples with a defined slope at intermediate points to form the output dynamic curve. The serial DAC is implemented to achieve higher order interpolation between the input sample points in the analog domain using switched capacitor CMOS circuits and without the use of a sample and hold circuit at the output. Conceptually, only two capacitors are needed for defining the output voltage for the conventional serial DAC. Dynamically programmable capacitor arrays define, via digital codes, the desired interpolation trajectory or output curve for the DAC between input sample points by defining the ratio of input charge Q(i) to the total capacitance C(i) at the i.sup.th time interval [Q(i)/C(i)]. The voltage at the output of the DAC is defined by incremental charge transfer at a defined rate between the input sample points. This technique uses minimum energy and area to define the dynamic curve for the DAC.

An object of the present invention is to generate a clock also before reception of a packet in a reception device. A reception device has: a storage unit storing a true time-stamp included in a received packet including audio data and the true time-stamp expressing reproduction time of the audio data; a timer counting time; a dummy time-stamp generation unit generating a dummy time-stamp as a false time-stamp; a comparator comparing time based on the true time-stamp stored in the storage unit or the dummy time-stamp and time indicated by the timer; and a clock generation unit generating a clock in accordance with a comparison result of the comparator. The comparator performs comparison using the dummy time-stamp until a predetermined condition is satisfied and, after the predetermined condition is satisfied, performs comparison using the true time-stamp.

An object of the present invention is to generate a clock also before reception of a packet in a reception device. A reception device has: a storage unit storing a true time-stamp included in a received packet including audio data and the true time-stamp expressing reproduction time of the audio data; a timer counting time; a dummy time-stamp generation unit generating a dummy time-stamp as a false time-stamp; a comparator comparing time based on the true time-stamp stored in the storage unit or the dummy time-stamp and time indicated by the timer; and a clock generation unit generating a clock in accordance with a comparison result of the comparator. The comparator performs comparison using the dummy time-stamp until a predetermined condition is satisfied and, after the predetermined condition is satisfied, performs comparison using the true time-stamp.

A circuit includes a first transistor and a second transistor having respective control terminals coupled to receive first and second bias voltages. A first electronic switch is coupled in series with, and between current paths of the first and second transistors to provide an output current line between a circuit output node and ground. A second electronic switch is selectively activated to a conductive state in order to provide a charge transfer current path between a bias node and a charge transfer node in the output current line. A third electronic switch is selectively activated to a conductive state in order to provide a charge transfer current path between the charge transfer node and the control terminal of the second transistor.

The invention relates to a method for controlling digital-to-analog converters (DAC), the method comprising: providing a plurality of digital-to-analog converters (DAC) of a multi-channel converter array wherein each DAC includes a separate clock generator; generating, by each clock generator, a RF carrier signal; converting, by each DAC, digital data signals into analog RF data signals based on the carrier signals of the corresponding clock generators; providing a separate control signal for each clock generator wherein the control signals comprise control information such that when the control signals are applied to the corresponding clock generators the different analog RF data signals provided at respective output terminals of each DAC comprise a pre-defined phase shift to each other; controlling the clock generator of each DAC directly and independently based on the provided control signals. The invention further relates to a converter arrangement RF transmit circuit arrangement.

The invention relates to a method for controlling digital-to-analog converters (DAC), the method comprising: providing a plurality of digital-to-analog converters (DAC) of a multi-channel converter array wherein each DAC includes a separate clock generator; generating, by each clock generator, a RF carrier signal; converting, by each DAC, digital data signals into analog RF data signals based on the carrier signals of the corresponding clock generators; providing a separate control signal for each clock generator wherein the control signals comprise control information such that when the control signals are applied to the corresponding clock generators the different analog RF data signals provided at respective output terminals of each DAC comprise a pre-defined phase shift to each other; controlling the clock generator of each DAC directly and independently based on the provided control signals. The invention further relates to a converter arrangement RF transmit circuit arrangement.