An analog circuit including a pair of input nodes and a pair of output nodes is coupled to a mismatch reduction circuit including an input node, an output node, a phase controller that times even and odd phases, an input switch, and an output switch. The input switch electrically connects the mismatch reduction circuit input node to a first node of the pair of analog circuit input nodes during each even phase and to electrically connects the mismatch reduction circuit input node to a second node of the pair of analog circuit input nodes during each odd phase. The output switch electrically connects a first node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each even phase and electrically connects a second node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each odd phase.

Various embodiments of the invention relate to a high accuracy phase shift apparatus. The phase shift apparatus comprises a voltage controlled analog phase shifter, a microcontroller unit (MCU) and a digital-to-analog converter (DAC). The MCU generates a digital control signal, which is converted into an analog control signal by the DAC to control the voltage controlled analog phase shifter to achieve desired phase shift angle. The phase shift apparatus may further incorporate a temperature sensor for temperature compensation. The output from the temperature sensor may be used to modify the reference voltage of the DAC, or alternatively be used to modify the digital control signal from the MCU. By incorporation digitalized control and temperature compensation to an analog phase shifter, the disclosed phase shift apparatus achieves high accuracy digitalized control, a flat phase shift over a wide bandwidth, and a stable phase shift over temperature variation.

Various embodiments of the invention relate to a high accuracy phase shift apparatus. The phase shift apparatus comprises a voltage controlled analog phase shifter, a microcontroller unit (MCU) and a digital-to-analog converter (DAC). The MCU generates a digital control signal, which is converted into an analog control signal by the DAC to control the voltage controlled analog phase shifter to achieve desired phase shift angle. The phase shift apparatus may further incorporate a temperature sensor for temperature compensation. The output from the temperature sensor may be used to modify the reference voltage of the DAC, or alternatively be used to modify the digital control signal from the MCU. By incorporation digitalized control and temperature compensation to an analog phase shifter, the disclosed phase shift apparatus achieves high accuracy digitalized control, a flat phase shift over a wide bandwidth, and a stable phase shift over temperature variation.

A source driver includes a digital-to-analog converter configured to receive a data signal, convert the received data signal into an analog signal, and output the analog signal, an output unit including amplifiers configured to amplify the analog signal, a control signal provision unit configured to output at least one control signal based on or in response to a first bias signal, at least one level shifter configured to shift a level of the control signal(s) based on or in response to a second bias signal having a higher voltage than the first bias signal and output at least one level-shifted control signal, and a protector configured to detect a voltage of the first bias signal and turn off the amplifiers and the level shifter when the detected voltage of the first bias signal is less than a predetermined reference voltage.

A source driver includes a digital-to-analog converter configured to receive a data signal, convert the received data signal into an analog signal, and output the analog signal, an output unit including amplifiers configured to amplify the analog signal, a control signal provision unit configured to output at least one control signal based on or in response to a first bias signal, at least one level shifter configured to shift a level of the control signal(s) based on or in response to a second bias signal having a higher voltage than the first bias signal and output at least one level-shifted control signal, and a protector configured to detect a voltage of the first bias signal and turn off the amplifiers and the level shifter when the detected voltage of the first bias signal is less than a predetermined reference voltage.

The disclosure is directed to an OFDM receiver with a low-resolution ADC and an electronic device thereof. According to one of the exemplary embodiments, the OFDM receiver may include not limited to: an ADC module which receives a transmission signal of a channel in an analog format and digitizes the transmission signal into a digital format to generate a quantized transmission signal; an error compensating and estimating module which is coupled to the ADC module, receives the quantized transmission signal and a feedback signal which is a first estimated time-domain transmission signal to generate an estimated error signal according to a turbo iterative updating technique; and a signal estimating module which is coupled to the error compensating and estimating module, receives the estimated error signal and a channel attenuation coefficient of the channel to generate an estimated transmission signal.

A process and corresponding system for encoding and decoding digital data in analog signals is disclosed. Digital data values are represented by concurrent combinations of distinct audio tones, which combine to create chords. The chords have multiple identifiable parameters that can be modulated to represent the data values. For instance, the modulated chords can include a concurrent combination of distinct tones that each have a different frequency and a different starting time. The frequencies of the tones and the starting times of those tones can be modulated to create unique combinations that represent respective data values. As such, analog audio content of a given chord can be used to represent a particular data value and the analog audio signals can be transmitted between nodes in a communication network in order to communicate that data value.

A wired transmitter includes a digital-to-analog converter (DAC) and a line driver. The DAC generates first output signals according to a digital code, wherein a first circuit in the DAC operates in a first voltage domain and a second circuit of the DAC operates in a second voltage domain, and an upper limit of the first voltage domain is lower than an upper limit of the second voltage domain. The line driver operates in the second voltage domain, and generates second output signals according to the first output signals. Each of the DAC and the line driver is implemented by transistors corresponding to the first voltage domain.

A wired transmitter includes a digital-to-analog converter (DAC) and a line driver. The DAC generates first output signals according to a digital code, wherein a first circuit in the DAC operates in a first voltage domain and a second circuit of the DAC operates in a second voltage domain, and an upper limit of the first voltage domain is lower than an upper limit of the second voltage domain. The line driver operates in the second voltage domain, and generates second output signals according to the first output signals. Each of the DAC and the line driver is implemented by transistors corresponding to the first voltage domain.

The present disclosure relates to a DAC that includes: a first pixel including a first transfer gate coupling a memory node of the first pixel and a capacitive sensing node (SN); a second pixel comprising a first transfer gate coupling a memory node of the second pixel and the capacitive SN; a reset transistor coupling the sensing node to a first voltage supply rail; and a control circuit configured to store electrical charge by activating the reset transistor to apply a reference voltage to the memory node of each of the first and second pixels; and generate a voltage of the DAC at the sensing node by deactivating the reset transistor and controlling the first transfer gates of the first and second pixels to transfer the charge stored.