The present disclosure relates to a DAC that includes: a first pixel including a first transfer gate coupling a memory node of the first pixel and a capacitive sensing node (SN); a second pixel comprising a first transfer gate coupling a memory node of the second pixel and the capacitive SN; a reset transistor coupling the sensing node to a first voltage supply rail; and a control circuit configured to store electrical charge by activating the reset transistor to apply a reference voltage to the memory node of each of the first and second pixels; and generate a voltage of the DAC at the sensing node by deactivating the reset transistor and controlling the first transfer gates of the first and second pixels to transfer the charge stored.

A surface ion trap comprising a plurality of electrodes and DACs, each electrode being controlled by a DAC, wherein a first set of DACs control the electrodes configured to trap an ion in a first area and a second set of DACs control the electrodes configured to trap an ion in a second area wherein the first set of DACs are configured to operate with low noise and low bandwidth and the second set of DACs are configured to operate with a high bandwidth and high noise.

A surface ion trap comprising a plurality of electrodes and DACs, each electrode being controlled by a DAC, wherein a first set of DACs control the electrodes configured to trap an ion in a first area and a second set of DACs control the electrodes configured to trap an ion in a second area wherein the first set of DACs are configured to operate with low noise and low bandwidth and the second set of DACs are configured to operate with a high bandwidth and high noise.

A neural network scheme is described that uses unsupervised learning in oscillator neural networks. Training occurs by varying the weights in proportion to the output from a frequency detector. Inputs and initial weights are split into plurality of inputs and plurality of weights. These split inputs and weights can be analog or digital. Oscillators generate signals having frequencies that represent difference in inputs, initial weights, and adjusted factors. Frequency detectors are used to compare the oscillator frequencies with a synchronized frequency of all oscillators. The output of the frequency detectors are used to generate the adjusted factors, and in turn generate trained weights.

A neural network scheme is described that uses unsupervised learning in oscillator neural networks. Training occurs by varying the weights in proportion to the output from a frequency detector. Inputs and initial weights are split into plurality of inputs and plurality of weights. These split inputs and weights can be analog or digital. Oscillators generate signals having frequencies that represent difference in inputs, initial weights, and adjusted factors. Frequency detectors are used to compare the oscillator frequencies with a synchronized frequency of all oscillators. The output of the frequency detectors are used to generate the adjusted factors, and in turn generate trained weights.

Devices, systems, and methods that include a qubit coupled to a projective-source digital-to-analog converter (PSDAC) for projective measurement of the qubit. A change in flux state of the PSDAC from a first flux state to a second flux state generates a fast-flux step or fast-step waveform that can be applied to the qubit to perform projective measurement of the qubit. For a quantum processor that includes a set of qubits wherein each qubit is coupled to a respective PSDAC, a shared trigger line can activate each PSDAC to generate a respective fast-flux step or fast-step waveform. Synchronization devices can synchronize the fast-flux steps or fast-step waveforms, allowing for projective readout of the set of qubits.

Devices, systems, and methods that include a qubit coupled to a projective-source digital-to-analog converter (PSDAC) for projective measurement of the qubit. A change in flux state of the PSDAC from a first flux state to a second flux state generates a fast-flux step or fast-step waveform that can be applied to the qubit to perform projective measurement of the qubit. For a quantum processor that includes a set of qubits wherein each qubit is coupled to a respective PSDAC, a shared trigger line can activate each PSDAC to generate a respective fast-flux step or fast-step waveform. Synchronization devices can synchronize the fast-flux steps or fast-step waveforms, allowing for projective readout of the set of qubits.

A chip and a chip test method are provided. The chip includes a receiver circuit and a test circuit. The receiver circuit includes a signal receiving unit and a signal bump. The signal bump is coupled to the signal receiving unit. The test circuit is coupled to a circuit node between the signal receiving unit and the signal bump. The test circuit includes a digital-to-analog converter, a first resistor, and a unit gain buffer. A first terminal of the first resistor is coupled to the circuit node. An output terminal of the unit gain buffer is coupled to a second terminal of the first resistor. A first input terminal of the unit gain buffer is coupled to an output terminal of the digital-to-analog converter. A second input terminal of the unit gain buffer is coupled to an output terminal of the unit gain buffer.

According to one aspect, an integrated circuit is provided comprising: a digital-to-analog converter (MDAC) configured to convert a digital word (DIGW) into an analog signal (SDAC), a switching circuit including: a first transistor (PMOS1) having a drain configured to receive the analog signal (SDAC) and a source connected to a drain of a second transistor (PMOS2) and a third transistor (NMOS1) having a drain configured to receive the analog signal (SDAC) and a source connected to a drain of a fourth transistor (NMOS2); a voltage control circuit configured to apply a voltage on the source of the first transistor (PMOS1) and on the source of the third transistor (NMOS1) so as to limit a drain-source voltage of the first transistor (PMOS1) and a drain-source voltage of the third transistor (NMOS1) regardless of the value of said digital word.

A magnetic flux bias circuit includes an input signal line to which an input signal indicating an applied magnetic flux using a digital value is input, a first current control line, a second current control line, and a third current control line to which a clock signal according to the input signal is input, a digital/analog conversion unit converting the input signal into an analog signal using a circuit including a quantum flux parametron circuit on the basis of the input signal input to the input signal line and the clock signal input to the first current control line, the second current control line, and the third current control line, and a magnetic flux application unit applying an applied magnetic flux to a controlled object on the basis of the analog signal output from the digital/analog conversion unit.