In described examples, a digital-to-analog converter includes an output, multiple most significant bit (MSB) connector resistors each having a resistance R??R, multiple least significant bit (LSB) connector resistors each having a resistance R, and multiple binary arm resistors each having a resistance 2R. The MSB connector resistors are coupled in a series beginning with the output and ending with a first one of the LSB connector resistors, and the LSB connector resistors are coupled in a series beginning with the first LSB connector resistor. A terminal of one of the binary arm resistors is coupled to an ending of the LSB connector resistor series, and a terminal of each of different remaining ones of the binary arm resistors is coupled between a different pair of the MSB and/or LSB connector resistors.

A digital-to-analog converter is provided. The digital-to-analog converter includes a delay circuit configured to iteratively delay a digital input signal based on a clock signal for generating a plurality of delayed digital input signals. Further, the digital-to-analog converter includes a plurality of groups of inverter cells. Each group of inverter cells is configured to generate a respective analog signal based on one of the plurality of delayed digital input signals. The inverter cells includes a respective inverter circuit configured to invert the respective delayed digital input signal. The plurality of groups of inverter cells include different numbers of inverter cells. The digital-to-analog converter additionally includes an output configured to output an analog output signal based on the analog signals of the plurality of groups of inverter cells.

A current mode end-to-end signal path includes, a digital to analog converter (DAC), operating in current mode and an upconverting mixer, operating in current mode and operatively coupled to the DAC, wherein analog inputs and analog outputs of the DAC and the upconverting mixer are represented as currents, and the DAC generates a baseband signal.

A current mode end-to-end signal path includes, a digital to analog converter (DAC), operating in current mode and an upconverting mixer, operating in current mode and operatively coupled to the DAC, wherein analog inputs and analog outputs of the DAC and the upconverting mixer are represented as currents, and the DAC generates a baseband signal.

A filter circuitry (200) using an active inductor is disclosed. The filter circuitry (200) has a first terminal (In1/Out1) and a second terminal (In2/Out2). The filter circuitry (200) comprises a first transistor (M1) and a second transistor (M2). The filter circuitry (200) further comprises a first switch (S1), a second switch (S2), a first capacitor (C1), a second capacitor (C2) and a resistor (R). The first and second transistors (M1/M2) together with the resistor (R) and the first and second switches (S1/S2) are connected in a current mirror topology. The first and second capacitors (C1/C2) are connected at the first and second terminals of the filter circuitry (200) respectively. The filter circuitry (200) is configurable to either have the first terminal (In1/Out1) as input and the second terminal (In2/Out2) as output or have the first terminal (In1/Out1) as output and the second terminal (In2/Out2) as input by changing on-off states of the first and second switches. The transistors are interconnected in a current-mirror fashion. Depending on the switch position one of the transistors also acts as part of an active inductor such that the circuit functions as a low pass filter with a complex pole pair and a real pole. Depending on the switch position the LPF allows signal flow in either direction. For use in a TDD environment in combination with a passive mixer (420).

A filter circuitry (200) using an active inductor is disclosed. The filter circuitry (200) has a first terminal (In1/Out1) and a second terminal (In2/Out2). The filter circuitry (200) comprises a first transistor (M1) and a second transistor (M2). The filter circuitry (200) further comprises a first switch (S1), a second switch (S2), a first capacitor (C1), a second capacitor (C2) and a resistor (R). The first and second transistors (M1/M2) together with the resistor (R) and the first and second switches (S1/S2) are connected in a current mirror topology. The first and second capacitors (C1/C2) are connected at the first and second terminals of the filter circuitry (200) respectively. The filter circuitry (200) is configurable to either have the first terminal (In1/Out1) as input and the second terminal (In2/Out2) as output or have the first terminal (In1/Out1) as output and the second terminal (In2/Out2) as input by changing on-off states of the first and second switches. The transistors are interconnected in a current-mirror fashion. Depending on the switch position one of the transistors also acts as part of an active inductor such that the circuit functions as a low pass filter with a complex pole pair and a real pole. Depending on the switch position the LPF allows signal flow in either direction. For use in a TDD environment in combination with a passive mixer (420).

A self-calibrating digital-to-analog converter (DAC) is disclosed. The self-calibrating DAC includes a DAC including a least significant bit (LSB) side resistor network and a most significant bit (MSB) side resistor network. At least the MSB side resistor network includes a plurality of trimmable resistors. A resistance to frequency converter coupled with an output of the DAC is included to generate a frequency f.sub.L based on a value of the LSB side resistor network or the MSB side resistor network. A monitor is included to generate a counter value by comparing f.sub.L with a high frequency clock having a constant frequency f.sub.H. A memory is included to store at least two counter values generating by comparing f.sub.L and f.sub.H once when the LSB side resistor network is connected while the MSB side resistor network is floating and once when the LSB side resistor network is floating while only one of the resistors in the MSB side resistor network is connected and all other resistors in the MSB side resistor network are floating. A comparator is included to compare the at least two counter values. A trimming controller is included to generate a trimming signal to trim one of the plurality of trimmable resistors based on an output of the comparator.

A self-calibrating digital-to-analog converter (DAC) is disclosed. The self-calibrating DAC includes a DAC including a least significant bit (LSB) side resistor network and a most significant bit (MSB) side resistor network. At least the MSB side resistor network includes a plurality of trimmable resistors. A resistance to frequency converter coupled with an output of the DAC is included to generate a frequency f.sub.L based on a value of the LSB side resistor network or the MSB side resistor network. A monitor is included to generate a counter value by comparing f.sub.L with a high frequency clock having a constant frequency f.sub.H. A memory is included to store at least two counter values generating by comparing f.sub.L and f.sub.H once when the LSB side resistor network is connected while the MSB side resistor network is floating and once when the LSB side resistor network is floating while only one of the resistors in the MSB side resistor network is connected and all other resistors in the MSB side resistor network are floating. A comparator is included to compare the at least two counter values. A trimming controller is included to generate a trimming signal to trim one of the plurality of trimmable resistors based on an output of the comparator.

A numerically controlled oscillator system for maintaining a consistent phase reference while switching data rates may include a numerically controlled oscillator (NCO) circuit. The NCO circuit may include a phase accumulator, a phase-to-signal mapping circuit, and a first free-running counter. The phase accumulator may receive a new phase value as an input in response to an update signal. The phase-to-signal mapping circuit may map a value from the phase accumulator to a periodic signal. The first free-running counter may continue counting, without being reset, while the numerically controlled oscillator system is switching digital data rates. The first free-running counter may be configured to provide the new phase value to the phase accumulator using a representation of a counter value of the first free-running counter and a frequency tuning word defined by a representation of a frequency of the periodic signal.

A controllable temperature coefficient bias (CTCB) circuit is disclosed. The CTCB circuit can provide a bias to an amplifier. The CTCB circuit includes a variable with temperature (VWT) circuit having a reference circuit and a control circuit. The control circuit has a control output, a first current control element and a second current control element. Each current control element has a controllable resistance. One of the two current control elements may have a relatively high temperature coefficient and another a relatively low temperature coefficient. A controllable resistance of one of the current control elements increases when the controllable resistance of the other current control element decreases. However, the total resistance of the current control circuit remains constant with a constant temperature. The VWT circuit has an output with a temperature coefficient that is determined by the relative amount of current that flows through each current control element of the control circuit. A Current Digital to Analog Converter (IDAC) scales the output of the VWT and provides the scaled output to an amplifier bias input.