The disclosure relates to a phase shifter having a first mode of operation and a second mode of operation, the phase shifter comprising a mixer stage configured to mix an oscillator signal with an analog signal to provide a phase shifted signal, switching circuitry and a controller arranged to provide the analog signal to the mixer stage as a voltage in the first mode of operation and as a current in the second mode of operation.

A smart sensor system can include one or more configurable input and output channels, each configurable channel including one or more switches configured to activate the input and/or output and/or to select a type of input and/or output signal, at least one analog-to-digital converter and at least one digital-to-analog converter operatively connected to the one or more switches for the one or more configurable channels, and at least one controller configured to control the configurable channels.

Devices and methods for digital to analog conversion (DAC) are provided, in which the analog outputs of an even number of digital to analog converters are combined. The individual converters operate on the same data but there is a relative time delay between the input digital signal received by one or more of the converters and the input digital signal received by other of the converters, wherein the delay is a fraction of the data sample period. Moreover, the data signal fed to half of the converters has an inverse relationship with the data signal fed to the other half of the converters and their analog outputs are subtracted. Dither and filtering techniques may also be employed.

Resistor mismatch may be digitally compensated based on a known resistor mismatch, power supply information, and/or other operating parameters of the amplifier. The digital compensation may be applied to the digital input signal before conversion for processing and amplification in the analog domain. An amplifier with digital compensation for resistor mismatch may be used in a class-D amplifier with a closed loop and feedforward feedback. A class-D or other amplifier with digital compensation may be integrated with electronic devices such as mobile phones.

Embodiments of the present invention provide a digital-to-analog conversion circuit, where the digital-to-analog conversion circuit includes a signal amplitude detector and a digital-to-analog converter. When the signal amplitude detector detects a low signal amplitude, a first current module in the digital-to-analog converter operates normally and a second current module in the digital-to-analog converter stops operating. In addition, when stopping operating, the second current module is in a state of a third bias voltage and a fourth bias voltage that are generated by a second bias circuit. When the amplitude detector detects a high signal amplitude subsequently, the second current module resumes normal operation. After operating normally, the second current module switches back to a first bias voltage and a second bias voltage that are generated by a first bias circuit. This reduces a nonlinearity problem caused before a second current module resumes normal operation.

Systems and methods are provided for managing dynamic element matching (DEM) in digital-to-analog converters (DACs). One or more parameters associated with the DAC and/or a signal being converted via the DAC; and based on the one or more parameters, conditions affecting dynamic element matching in the DAC may be assessed. Based on the assessing of the conditions, one or more adjustments may be determined and dynamically applied to the dynamic element matching in the DAC.

Certain aspects of the present disclosure are directed to a digital predistortion (DPD) device for use within a wireless transmitter that permits the use of a downstream digital-to-analog converter that operates at a clock rate close to the bandwidth of a digital baseband input signal. In some examples, a sampling rate of a digital baseband input signal is increased using an upsampler to obtain an increased rate digital input signal. Predistortion is applied to the increased rate digital input signal using a DPD device to obtain a predistorted digital signal. The sampling rate of the predistorted digital signal is then decreased using a downsampler to obtain a lower-rate predistorted digital signal with a sampling rate below the increased rate of the upsampler (e.g. close to the bandwidth of a digital baseband input signal). A low pass filter may be provided to filter out-of-band signal components from the predistorted digital signal.

Various implementations described herein are directed to an integrated circuit. The integrated circuit may include converter circuitry that operates to provide a drive current. The integrated circuit may include process detector circuitry having multiple drive strength devices that are driven by the drive current from the converter circuitry. The multiple drive strength devices may provide multiple drive strength signals based on the drive current. The integrated circuit may include comparator circuitry having a comparator that receives the multiple drive strength signals from the multiple drive strength devices, detects a voltage difference between the multiple drive strength signals, and provides an output signal based on the detected voltage difference.

Some embodiments include apparatus and methods using a first digital-to-time converter (DTC) circuit to receive an input clock signal and generate a first clock signal based on the input clock signal, a second DTC circuit to receive the input clock signal and generate a second clock signal based on the input clock signal, and an output circuit to receive the first and second clock signals to generate an output clock signal based on the first and second clock signals.

An example capacitive digital-to-analog converter (CDAC) includes: a first plurality of capacitors consisting of M1 capacitors, where M is an integer greater than one, the first plurality of capacitors including top plates coupled to a first node; a second plurality of capacitors consisting of M1 capacitors, the second plurality of capacitors including top plates coupled to a second node; a first plurality of switches consisting of M1 switches coupled to bottom plates of the respective M1 capacitors of the first plurality of capacitors, the first plurality of switches further coupled to a third node providing a supply voltage and a fourth node providing a ground voltage; a second plurality of switches consisting of M1 switches coupled to bottom plates of the respective M1 capacitors of the second plurality of capacitors, the second plurality of switches coupled to the third node and the fourth node; and a control circuit including an input consisting of M bits for receiving an M bit code and an output consisting of 2*(M1) bits for providing a first M1 bit code to respectively control the M1 switches of the first plurality of switches and a second M1 bit code to respectively control the M1 switches of the second plurality of switches.