An example capacitive digital-to-analog converter (CDAC) includes: a first plurality of capacitors consisting of M1 capacitors, where M is an integer greater than one, the first plurality of capacitors including top plates coupled to a first node; a second plurality of capacitors consisting of M1 capacitors, the second plurality of capacitors including top plates coupled to a second node; a first plurality of switches consisting of M1 switches coupled to bottom plates of the respective M1 capacitors of the first plurality of capacitors, the first plurality of switches further coupled to a third node providing a supply voltage and a fourth node providing a ground voltage; a second plurality of switches consisting of M1 switches coupled to bottom plates of the respective M1 capacitors of the second plurality of capacitors, the second plurality of switches coupled to the third node and the fourth node; and a control circuit including an input consisting of M bits for receiving an M bit code and an output consisting of 2*(M1) bits for providing a first M1 bit code to respectively control the M1 switches of the first plurality of switches and a second M1 bit code to respectively control the M1 switches of the second plurality of switches.

The present disclosure relates to a digital-to-analog converter (DAC) linearization system including a DAC, a summing buffer structure, an analog-to-digital converter (ADC), a calculation system, an error look-up table, and an adder. A combination of the DAC, the summing buffer structure, and the ADC sequentially provide first and second ADC output signals, both of which include DAC integral nonlinearity (INL). The calculation system calculates the DAC INL based on the first and second ADC output signals, the error look-up table provides a correction signal mapping to the calculated DAC INL, and the adder provides a calibrated digital input signal to the DAC based on the correction signal. The calibrated digital input signal ensures the DAC to generate an updated output signal with less nonlinearity and improved purity.

The present disclosure relates to a digital-to-analog converter (DAC) linearization system including a DAC, a summing buffer structure, an analog-to-digital converter (ADC), a calculation system, an error look-up table, and an adder. A combination of the DAC, the summing buffer structure, and the ADC sequentially provide first and second ADC output signals, both of which include DAC integral nonlinearity (INL). The calculation system calculates the DAC INL based on the first and second ADC output signals, the error look-up table provides a correction signal mapping to the calculated DAC INL, and the adder provides a calibrated digital input signal to the DAC based on the correction signal. The calibrated digital input signal ensures the DAC to generate an updated output signal with less nonlinearity and improved purity.

A neural network unit cell circuit includes multiple floating gate transistors, each of the floating gate transistors having a first source/drain adapted for connection to a common bit line coupled with the unit cell circuit and having a gate adapted for connection to a corresponding one of a plurality of word lines coupled with the unit cell circuit. The unit cell further includes a resistor network having a plurality of resistors connected in a series ladder arrangement, with each node between adjacent resistors operatively connected to a second source/drain of a corresponding one of the floating gate transistors. The resistor network has a first terminal connected to a first voltage source. A readout transistor in the unit cell has a gate coupled with a second terminal of the resistor network, and has first and second source/drains generating an output voltage of the unit cell.

Data weighted averaging of a thermometric coded input signal is accomplished by controlling the operation of a crossbar switch matrix to generate a current cycle of a data weighted averaging output signal using a control signal generated in response to feedback of a previous cycle of the data weighted averaging output signal. The control signal specifies a bit location for a beginning logic transition of the data weighted averaging output signal in the current cycle based on detection of an ending logic transition of the data weighted averaging output signal in the previous cycle.

A digital/analog converter circuit includes: a decoding unit that performs decoding processing on a bit signal in a predetermined part of a digital signal; and a selector circuit that selects and outputs a voltage depending on an output of the decoding unit, in which a switching device is disposed on at least one of inside of the decoding unit and an output unit side of the decoding unit, the switching device being controlled by a control signal different from the hit signal as a target for the decoding processing.

A digital/analog converter circuit includes: a decoding unit that performs decoding processing on a bit signal in a predetermined part of a digital signal; and a selector circuit that selects and outputs a voltage depending on an output of the decoding unit, in which a switching device is disposed on at least one of inside of the decoding unit and an output unit side of the decoding unit, the switching device being controlled by a control signal different from the hit signal as a target for the decoding processing.

In a system, known digitizer signals (known analog signals or digital representations of known analog signals) are generated. The known digitizer signals are input into digitizers (analog-to-digital converter (ADCs) or digital-to-analog converter (DACs)) to output generated digitizer signals (generated digital representations or generated analog signals). The generated digitizer signals are analyzed in relation to the known digitizer signals to generate coupling coefficients, which can be either scalar quantities or finite-impulse-response (FIR) filter functions. Subsequent digitizer signals are generated. The subsequent digitizer signals are modified using the coupling coefficients to generate modified digitizer signals according to formulae. The modified digitizer signals are used directly as digital representations, or are input to the DACs to output modified analog signals that substantially match subsequent analog signals.

An analog video signal supply circuit includes a processing circuit that supplies first and second digital video signals. First and second digital-to-analog converters convert digital signals to analog signals. A control circuit controls operation in a first configuration where the first digital video signal is applied to an input of the first digital-to-analog converter and the second digital video signal to an input of the second digital-to-analog converter. The control circuit further controls operation in a second configuration where the first digital video signal is simultaneously applied to the inputs of the first and second digital-to-analog converters.

An analog video signal supply circuit includes a processing circuit that supplies first and second digital video signals. First and second digital-to-analog converters convert digital signals to analog signals. A control circuit controls operation in a first configuration where the first digital video signal is applied to an input of the first digital-to-analog converter and the second digital video signal to an input of the second digital-to-analog converter. The control circuit further controls operation in a second configuration where the first digital video signal is simultaneously applied to the inputs of the first and second digital-to-analog converters.