An apparatus for detecting object features can include: a probe signal transmitter configured to load a digital intermediate frequency signal onto a carrier signal, and to transmit a loaded signal outwards; an echo signal receiver configured to receive an echo signal, and to extract an object feature signal by performing respective down conversions on a quadrature signal of the carrier signal and a quadrature signal of the digital intermediate frequency signal; and a signal processor configured to identify object features according to the object feature signal.

An apparatus for detecting object features can include: a probe signal transmitter configured to load a digital intermediate frequency signal onto a carrier signal, and to transmit a loaded signal outwards; an echo signal receiver configured to receive an echo signal, and to extract an object feature signal by performing respective down conversions on a quadrature signal of the carrier signal and a quadrature signal of the digital intermediate frequency signal; and a signal processor configured to identify object features according to the object feature signal.

A novel and useful variable step serial DAC having a desired trajectory between input samples with a defined slope at intermediate points to form the output dynamic curve. The serial DAC is implemented to achieve higher order interpolation between the input sample points in the analog domain using switched capacitor CMOS circuits and without the use of a sample and hold circuit at the output. Conceptually, only two capacitors are needed for defining the output voltage for the conventional serial DAC. Dynamically programmable capacitor arrays define, via digital codes, the desired interpolation trajectory or output curve for the DAC between input sample points by defining the ratio of input charge Q(i) to the total capacitance C(i) at the i.sup.th time interval [Q(i)/C(i)]. The voltage at the output of the DAC is defined by incremental charge transfer at a defined rate between the input sample points. This technique uses minimum energy and area to define the dynamic curve for the DAC.

A configuration circuit for obtaining a digital code includes a controller circuit that generates a plurality of multibit control words. A digitally controlled current source circuit receives a multibit control word generated by the controller circuit. The digitally controlled current source circuit generates an output current that corresponds to the multibit control word in accordance with a predetermined output curve. A test voltage node receives the output current, and a test voltage develops in response to the output current. A reference voltage node develops a reference voltage, the level of which is independent of the multibit control word. A voltage comparison circuit (i) receives the test voltage and the reference voltage, (ii) compares the two voltages to produce a comparison result and (iii) sends the comparison result to the controller circuit. The digital code is obtained by the configuration circuit using the comparison result and the multibit control word.

A system is provided for interfacing a Full Authority Digital Engine Control (FADEC) system with engine sensors and actuators using miniaturized Low Temperature Co-fired Ceramic (LTCC) substrates operating as smart notes that communicate digitally over a data bus to a miniaturized LTCC operating as a data concentrator. The use of smart nodes and/or data concentrators assembled on LTCC substrates provides enhanced thermal and vibration performance along with resistance to hydration, improved reliability and reduced overall size of the circuitry unit.

A system is provided for interfacing a Full Authority Digital Engine Control (FADEC) system with engine sensors and actuators using miniaturized Low Temperature Co-fired Ceramic (LTCC) substrates operating as smart notes that communicate digitally over a data bus to a miniaturized LTCC operating as a data concentrator. The use of smart nodes and/or data concentrators assembled on LTCC substrates provides enhanced thermal and vibration performance along with resistance to hydration, improved reliability and reduced overall size of the circuitry unit.

An example method for fast ramp start-up during analog to digital conversion (ADC) includes opening a feedback bypass switch coupled to an amplifier to initiate an ADC operation, providing an injection current pulse to an inverting input of the amplifier, where the non-inverting input is coupled to a feedback bypass switch, integrating a first reference current coupled to the inverting input of the amplifier, where the integrating of the first reference current occurs due to the opening of the feedback bypass switch, and providing a reference voltage in response to the injection current pulse, the integrating of the first reference current, and a reference voltage coupled to a non-inverting input of the amplifier, where a level of the reference voltage is increased at least at initiation of the ADC operation in response to the injection current pulse.

An A/D converter includes: an input unit configured to receive an analog input signal, a preprocessing unit configured to convert the input signal into a digital preprocessing signal based on a dynamic range of the input signal and a first resolution corresponding to a predetermined first bit number, a first conversion unit configured to convert the preprocessing signal into a first output signal based on a second resolution corresponding to a second bit number smaller than the first bit number, and a second conversion unit configured to convert the preprocessing signal into a second output signal based on a third resolution corresponding to a third bit number which is smaller than the first bit number and is different from the second bit number.

A switching digital-to-analog converter (DAC) includes a logic gate for receiving a digital input signal having rising and falling edges defining an input pulse width, and outputting an offset input signal having rising and falling edges defining a mismatched pulse width different from the input pulse width due to relative movement of the rising and falling edges in response to a voltage offset introduced by the logic gate. A DC voltage source provides a direct current (DC) calibration signal, and a summer adds the DC calibration signal and the offset input signal to compensate for the voltage offset introduced by the logic gate, and to provide a corrected input signal. A unit DAC receives the corrected input signal, and selectively switches current to an output of the switching DAC in response to voltage values of the corrected input signal to provide an analog output.

A mobile docking station (MDS) includes a surface through which the MDS can electrically and communicatively couple to a handheld mobile device (HMD) while remaining physically unattached from the MDS. The MDS power circuitry configured to electrically couple the MDS and the HMD while a surface of the HMD physically contacts the surface of the MDS, wherein the electrical coupling enables transferring of power between the MDS and the HMD. The MDS also includes communications circuitry configured to communicatively couple the MDS and the HMD while the surface of the HMD physically contacts the surface of the MDS, wherein the communicative coupling enables unidirectional or bidirectional communications between the MDS and HMD.