A system includes a non-transitory memory, a processor in operable communication with the memory, a digital-to-analog converter (DAC) and a transmitter. The memory stores bit position information associated with a first data. The bit position information includes absolute position data and relative position data for each bit of a plurality of bits of the first data. The processor can receive a data stream including the first data, and compress the first data to generate a second data representing the first data. The second data has a data structure that is arranged based on: (1) the first data, and (2) the bit position information. The DAC can receive a digital representation of the second data from the processor and convert the digital representation of the second data into an analog representation of the second data. The transmitter can then transmit the analog representation of the second data.

This invention discloses a data processing circuit and a data processing method. The data processing method controls data transmission between a USB control unit and a USB interface, and includes the steps of: detecting a voltage of a configuration channel pin of the USB interface to generate a detection signal; determining whether the USB control unit and the USB interface are connected according to the detection signal; and performing an audio signal processing procedure when the USB control unit and the USB interface are not connected.

This invention discloses a data processing circuit and a data processing method. The data processing method controls data transmission between a USB control unit and a USB interface, and includes the steps of: detecting a voltage of a configuration channel pin of the USB interface to generate a detection signal; determining whether the USB control unit and the USB interface are connected according to the detection signal; and performing an audio signal processing procedure when the USB control unit and the USB interface are not connected.

An analog circuit including a pair of input nodes and a pair of output nodes is coupled to a mismatch reduction circuit including an input node, an output node, a phase controller that times even and odd phases, an input switch, and an output switch. The input switch electrically connects the mismatch reduction circuit input node to a first node of the pair of analog circuit input nodes during each even phase and to electrically connects the mismatch reduction circuit input node to a second node of the pair of analog circuit input nodes during each odd phase. The output switch electrically connects a first node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each even phase and electrically connects a second node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each odd phase.

An analog circuit including a pair of input nodes and a pair of output nodes is coupled to a mismatch reduction circuit including an input node, an output node, a phase controller that times even and odd phases, an input switch, and an output switch. The input switch electrically connects the mismatch reduction circuit input node to a first node of the pair of analog circuit input nodes during each even phase and to electrically connects the mismatch reduction circuit input node to a second node of the pair of analog circuit input nodes during each odd phase. The output switch electrically connects a first node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each even phase and electrically connects a second node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each odd phase.

According to an aspect of the inventive concept, there is provided an apparatus for processing an output signal of an analog-digital converter, includes: a first frequency conversion unit for converting a frequency of the output signal of the analog-digital converter so that a band where spurious components exist moves to a band where direct current components exist in the output signal of the analog-digital converter; a spurious component blocking unit for eliminating, from an output signal of the first frequency conversion unit, spurious components which have moved to the band where direct current components exist; and a second frequency conversion unit for restoring a frequency of an output signal of the spurious component blocking unit to the original frequency of the output signal of the analog-digital converter.

Systems and methods are provided for digital-to-analog converters (DACs) with enhanced dynamic element matching (DEM) and calibration. DEM may be adapted based on assessment of one or more conditions that may affect the DACs or DEM functions thereof. The one or more condition may comprise amount of signal backoff. The adaption may comprise switching the DEM function (as a whole, or partiallye.g., individual DEM elements) on or off based on the assess conditions. The DACs may incorporate use of calibration. The DEM and/or the calibration may be applied to only a portion of the DAC, such as a particular segment (e.g., a middle segment comprising bits between the MSBs and the LSBs).

A digital to analog converter (DAC) circuit is disclosed which employs isolation providing cascode devices to reduce data dependent signal distortion. A DAC circuit configured according to an embodiment includes a current source associated with each bit of a digital word that is to be converted. Each current source is coupled to a current switch that is controlled by the associated bit. The DAC also includes a cascode device coupled to each of the current switches through a feed line. The DAC further includes a summing junction configured to generate an analog output signal corresponding to the digital word based on a sum of currents provided by the current sources, through the current switches and the feed lines. The cascode devices provide impedance matching and isolation between the feed lines and the summing junction to reduce signal reflections between the current switches and the summing junction to improve conversion performance.

A digital-to-analog converter (DAC) controller system may be configured for controlling switching in an associated digital-to-analog converter (DAC), based on a plurality of system inputs that include at least a first system input corresponding to an input applied to the DAC for controlling switching therein, and a second system input that includes a reference control signal. The DAC controller system may include a logic gate circuit that generates a gate output based on two gate inputs that include the first system input and an input set based on the second system input; and a plurality of timing circuits that generate timing outputs for controlling timing of switching in the DAC, which include at least one timing circuit that generates a timing output based on the gate output, with the timing output configured for application in conjunction with and for adjusting a timing output of another timing circuit.

An envelope tracking system for controlling a power amplifier supply voltage includes envelope circuitry and a feed forward digital to analog converter (DAC) circuitry. The envelope circuitry is configured to generate a target envelope signal based on a selected power amplifier supply voltage. The feed forward DAC circuitry includes a voltage source circuitry and a selector circuitry. The voltage source circuitry is configured to generate a plurality of voltages. The selector circuitry is configured to select one of the plurality of voltages based at least on the target envelope signal. The feed forward DAC circuitry is configured to provide the selected voltage to a supply voltage input of a power amplifier that amplifies a radio frequency (RF) transmit signal.