A mixed signal receiver includes a first sample and hold (S/H) circuit having a first S/H input terminal to receive an analog input signal and a first S/H output terminal directly coupled to a first common node; a first data slicer having a first slicer input terminal coupled to the first common node; and a first data-driven charge coupling digital-to-analog converter (DAC) including: (i) a DAC input terminal to receive a first digital signal from a first digital output of the first data slicer, (ii) a DAC output terminal directly coupled to the first common node, (iii) a plurality of capacitor modules configured to be pre-charged during a sample phase, and (iv) logic components, wherein when the logic components toggle a voltage on the plurality of capacitor modules, charge is capacitively coupled to or from the first common node during an immediately subsequent hold phase.

The present application discloses a switching power supply using a transformer for transmitting information. The switching power supply includes an encoding and controlling circuit configured for generating an encoded signal based on output information of the secondary side and demand information of an electrical equipment, and modulating the encoded signal onto a switch voltage waveform; a primary chip, configured to obtain the induced switch voltage waveform from the auxiliary winding; a decoding and controlling circuit configured for decoding the modulated switching voltage waveform; and a loop control and drive module configured to control on/off of the primary side switch tube according to decoded results to adjust the secondary side output information.

The present application discloses a switching power supply using a transformer for transmitting information. The switching power supply includes an encoding and controlling circuit configured for generating an encoded signal based on output information of the secondary side and demand information of an electrical equipment, and modulating the encoded signal onto a switch voltage waveform; a primary chip, configured to obtain the induced switch voltage waveform from the auxiliary winding; a decoding and controlling circuit configured for decoding the modulated switching voltage waveform; and a loop control and drive module configured to control on/off of the primary side switch tube according to decoded results to adjust the secondary side output information.

An electronic device may include wireless circuitry having a mixer configured to receive an oscillating signal from oscillator circuitry. The oscillator circuitry can include a chain of buffer circuits referred to as oscillator driver circuitry. Transformers may be coupled at the input and output of each buffer circuit in the chain. Adjustable biasing circuits may be coupled at the input of a selected buffer circuit in the chain. The adjustable biasing circuits can be digital-to-analog converters (DACs) configured to apply a differential direct current (DC) offset voltage to the input of the selected buffer circuit. The differential DC offset voltage can have a value that minimizes a second harmonic component of the oscillator driver circuitry.

An electronic device may include wireless circuitry having a mixer configured to receive an oscillating signal from oscillator circuitry. The oscillator circuitry can include a chain of buffer circuits referred to as oscillator driver circuitry. Transformers may be coupled at the input and output of each buffer circuit in the chain. Adjustable biasing circuits may be coupled at the input of a selected buffer circuit in the chain. The adjustable biasing circuits can be digital-to-analog converters (DACs) configured to apply a differential direct current (DC) offset voltage to the input of the selected buffer circuit. The differential DC offset voltage can have a value that minimizes a second harmonic component of the oscillator driver circuitry.

The invention concerns a circuit for transferring a data from one clock domain to another clock domain, the circuit comprising: a digital circuit configured to generate a data signal synchronized with a source clock signal, and to receive such data by sampling the data signal synchronized with a target clock signal; a phase comparator which is configured to determine a phase relationship between the source clock signal and the target clock signal; and a data signal synchronization circuit configured to receive data signal transitions that are synchronized with the source clock signal, and to provide a synchronized data signal transitions of which are synchronized with the target clock signal.

The invention concerns a circuit for transferring a data from one clock domain to another clock domain, the circuit comprising: a digital circuit configured to generate a data signal synchronized with a source clock signal, and to receive such data by sampling the data signal synchronized with a target clock signal; a phase comparator which is configured to determine a phase relationship between the source clock signal and the target clock signal; and a data signal synchronization circuit configured to receive data signal transitions that are synchronized with the source clock signal, and to provide a synchronized data signal transitions of which are synchronized with the target clock signal.

A method for a multichannel geophysical data acquisition system is provided in the field of electrical resistivity tomography. Individual and autonomous node operating systems are provided. Separate communication channels for upstream and downstream data transfer, high voltage transfer and synchronization signals are provided. A novel use of high voltage isolation barriers is also provided. A direct memory access data transfer process is provided.

A method for a multichannel geophysical data acquisition system is provided in the field of electrical resistivity tomography. Individual and autonomous node operating systems are provided. Separate communication channels for upstream and downstream data transfer, high voltage transfer and synchronization signals are provided. A novel use of high voltage isolation barriers is also provided. A direct memory access data transfer process is provided.

An MRAM-based vector multiplication device, such as can be used for inferencing in a neural network, is presented that is ultralow power, low cost, and does not require special on-chip programming. A crosspoint array has an MRAM cell at each crosspoint junction and periphery array circuitry capable of supplying independent input voltages to each word line and reading current on each bit line. Vector multiplication is performed as an in-array multiplication of a vector of input voltages with matrix weight values encoded by the MRAM cell states. The MRAM cells can be individually programmed using a combination of input voltages and an external magnetic field. The external magnetic field is chosen so that a write voltage of one polarity reduces the anisotropy sufficiently to align the cell state with the external field, but is insufficient to align the cell if only half of the write voltage is applied.