The disclosure provides a circuit. The circuit includes an amplifier and a digital to analog converter (DAC). The amplifier receives a reference voltage at an input node of the amplifier. The DAC is coupled to the amplifier through a refresh switch. The DAC includes one or more current elements. Each current element of the one or more current elements receives a clock. The DAC includes one or more switches corresponding to the one or more current elements. A feedback switch is coupled between the one or more switches and a feedback node of the amplifier. The DAC provides a feedback voltage at the feedback node of the amplifier.

In some embodiments, an apparatus comprises a device clock configured to generate a device clock signal a synchronization (SYSREF) clock generation circuit configured to receive the device clock signal from the device clock. The SYSREF clock generating circuit comprises a SYSREF divider configured to generate a SYSREF clock at least partially according to the device clock signal, an interpolator configured to generate a shifted clock at least partially according to the device clock signal, and a latch coupled to the SYSREF divider and the interpolator and configured to sample the SYSREF clock at a rising edge of the shifted clock.

Multiplexing circuitry and method for driving multiplexing circuits are provided. A circuit includes a multiplexer circuit having symmetrical data input paths driven by a half-rate clock signal and a first stage multiplexing circuit configured to provide input signals to the multiplexer circuit. The first stage multiplexing circuit is driven by quadrature clocks to generate time-shifted data.

Multiplexing circuitry and method for driving multiplexing circuits are provided. A circuit includes a multiplexer circuit having symmetrical data input paths driven by a half-rate clock signal and a first stage multiplexing circuit configured to provide input signals to the multiplexer circuit. The first stage multiplexing circuit is driven by quadrature clocks to generate time-shifted data.

Methods and systems are provided for dynamic power switching in current-steering digital-to-analog converters (DACs). A DAC circuit may be configured to apply digital-to-analog conversions based on current steering, and to particularly incorporate use of dynamic power switching during conversions. The DAC circuit may comprise a main section, which may connect a main supply voltage to a main current source. The main section may comprise a positive-side branch and a negative-side branch, which may be configured to steer positive-side and negative-side currents, such as in a differential manner, to effectuate the conversions. The dynamic power switching may be applied, for example, via a secondary section connecting a main current source in the DAC circuit to a secondary supply voltage. The secondary supply voltage may be configured such that it may be less than the main supply voltage used in driving the current steering in the DAC circuit.

Methods and systems are provided for dynamic power switching in current-steering digital-to-analog converters (DACs). A DAC circuit may be configured to apply digital-to-analog conversions based on current steering, and to particularly incorporate use of dynamic power switching during conversions. The DAC circuit may comprise a main section, which may connect a main supply voltage to a main current source. The main section may comprise a positive-side branch and a negative-side branch, which may be configured to steer positive-side and negative-side currents, such as in a differential manner, to effectuate the conversions. The dynamic power switching may be applied, for example, via a secondary section connecting a main current source in the DAC circuit to a secondary supply voltage. The secondary supply voltage may be configured such that it may be less than the main supply voltage used in driving the current steering in the DAC circuit.

A method in a transmitter circuit of generating a signal comprising a first sequence of OFDM symbols, which are to be transmitted within a frequency sub band of a second sequence of OFDM symbols is disclosed. A first cyclic prefix (CP) of the second sequence of OFDM symbols has a first duration, and a second CP of the second sequence of OFDM symbols has a second duration. In order to generate both the first and the second cyclic prefix with an integer number of equidistant samples, a first sampling rate is required. The method comprises generating the signal comprising the first sequence of OFDM symbols at a second sampling rate, lower than the first sampling rate, and adjusting a sampling phase during CPs.

A D/A converter converts digital audio data D.sub.IN into analog differential audio signals V.sub.P and V.sub.N. A differential to single-ended conversion circuit converts the differential audio signals V.sub.P and V.sub.N into a single-ended audio signal V.sub.SE. A volume circuit receives the single-ended audio signal V.sub.SE, and amplifies the single-ended audio signal V.sub.SE with a gain that corresponds to a volume value. A reference voltage source generates a reference voltage V.sub.REF commonly referred by the differential to single-ended conversion circuit and the volume circuit. In a calibration operation, a calibration circuit controls the D/A converter so as to shift at least one from among the differential audio signals V.sub.P and V.sub.N such that the difference between the output voltage V.sub.SE of the differential to single-ended conversion circuit and the reference voltage V.sub.REF approaches zero.

A D/A converter converts digital audio data D.sub.IN into analog differential audio signals V.sub.P and V.sub.N. A differential to single-ended conversion circuit converts the differential audio signals V.sub.P and V.sub.N into a single-ended audio signal V.sub.SE. A volume circuit receives the single-ended audio signal V.sub.SE, and amplifies the single-ended audio signal V.sub.SE with a gain that corresponds to a volume value. A reference voltage source generates a reference voltage V.sub.REF commonly referred by the differential to single-ended conversion circuit and the volume circuit. In a calibration operation, a calibration circuit controls the D/A converter so as to shift at least one from among the differential audio signals V.sub.P and V.sub.N such that the difference between the output voltage V.sub.SE of the differential to single-ended conversion circuit and the reference voltage V.sub.REF approaches zero.

A method of processing an input voltage. The method includes, during a sampling phase, using a digital-to-analog converter (DAC) capacitor to sample a reference voltage. The method includes, during a charge redistribution phase, using an input voltage to charge the DAC capacitor.